1. Proposed Roadmap Tables on STRJ-WG1
SOC Design Productivity, SOC Low Power, and DSM related issues
STRJ-WG1
March 2000
February 9,

2. Contents (1)SOC Design Productivity
Assumptions and study reaching to the table
P.3 - P.9
SOC Design Productivity Table
P.10
(2)SOC Low Power
Assumptions and study reaching to the table
P.11 - P.17
SOC Low Power Table
P.18
Potential solution map
P.19 - p.20
(3)DSM Related Issues
An overall DSM requirements table
P.21 - p.22
Assumptions and study reaching to the table
for each DSM issue those are Crosstalk noise,
RC delay, EMI, IR drop and Electro-migraton
P.23 - p.30
February 9,

3. SOC Design Productivity
Premises
Technology Node, ASIC Usable Transistors, and DRAM capacity
conform to ITRS99 ORTC.
Die size remains around 10mm
Application is not specified, but surely it is high-end SOC
in each generation.
Prospects
Logic gate count ratio continuously decreases from 80%(1999) thru
50%(2002), 35%(2005), into 15%(2011).
Contrarily, re-use circuit ratio within Logic gate count grows from 20%
(1999), thru 50%(2002), 70%(2005), to be 90%(2011) .
Power supply voltage goes down from 1.5V(1999) to 0.5V(2011) .
Operation frequency goes up from 150MHz(1999) to 2000MHz(2011) .
February 9,

4. SOC Design Productivity(cont.)
Assumptions
Total design resource is in proportion to size of newly designed
circuit, e.g. 1Man*Year as 360Kgates.
There now exists approximately 50% design overhead for re-use
circuit, namely it costs 50% of design resource with same size newly
designed circuit.
Contribution from both productivity improvement for Newly designed
circuit and Overhead reduction for Re-use circuit are considered
as gate size reduction for each circuit in accordance with amount of
improvement and overhead reduction, respectively.
February 9,

5. SOC Design Productivity(cont.)
Productivity Requirement
Total required design resource is unchangingly kept around 10 Man*Year.
Solution to be accomplished
Both 30% improvement per every 3 years for newly designed circuit
and 30% improvement per every 3 years for design overhead for re-use
circuit are needed to be accomplished.
February 9,

6. SOC Design Productivity(cont.)
SOC consists of Logic blocks and existing
hard IP(mainly Memory)
Logic block
Existing hard IP
Each logic block can be implemented
by newly designed portion and re-use
portion such as IPs
Newly designed portion
Re-use portion
February 9,

7. SOC Design Productivity(cont.)
Total logic gate count
and Newly/Re-use ratio
Total gate count
and Logic/Non-Logic ratio
MGates
MGates
February 9,

8. SOC Design Productivity(cont.)
How to derive “Total Design Resource” and
“Target Design Resource”
Total Design Resource( M gates)
= #(Newly designed circuit) x [Productivity improvement(%)]
+ #(Re-use circuit) x [Overhead in Re-use circuit(%)]
Target Design Resource( Man * Year)
= (Total Design Resource) / (Normalized unit Man*Year productivity)
here, “Normalized unit Man*Year productivity” is assumed as 0.36M gates
(Ex.) in 2005
Total Design Resource( M gates)
= (11.64 x ( ) ) x (11.64 x 0.7 ) x = 3.67 M gates
Hence, Target Design Resource( Man * Year)
= / = Man * Year
February 9,

9. SOC Design Productivity(cont.)
Man*Years 50 45 40 35 30 25 20 15 10 5
1999
2002
2005
2011
Target
No-imp
Case A
Case B
No-imp : in case of No improvement
Case A : in case of achieving improvement only for Newly designed circuit
Case B : in case of achieving improvement only for Re-use overhead
February 9,

10. SOC Design Productivity Table
Unit
1999
2002
2005
2011
Technology Node nm
180
130
100 50
ASIC Usable Transistors
M Tr./cm2 20 54
133
811
(*1)
Logic gate count ratio in area %
80%
50%
35%
15%
Logic Gate count
M gates
4.00
6.75
11.64
30.41
DRAM (Production)
M bits/cm2
200
525
1,230
7,510
(*1)
Embedded Memory size
M bits 16
105
319.8
2,553
Power supply voltage V
1.5
1.2
0.9
0.5
Operation Frequency
MHz
150
400
1000
2000
Design Resource
(ratio) 1
1.7
2.9
7.6
Re-use circuit ratio %
20%
50%
70%
90%
Newly designed circuit
M gates
3.20
3.38
3.49
3.04
Productivity improvement %
100%
70%
49%
24.%
(*2)
Resource for Newly designed(A)
M gates
3.20
2.36
1.71
0.73
Overhead in Re-use circuit %
50%
35%
24%
12%
(*3)
Resource for Re-use circuit(B)
M gates
0.40
1.18
2.00
3.29
Total Design resource(A+B)
M gates
3.60
3.54
3.67
4.02
Target Design Resource
Man*Years 10
9.8
10.2
11.2
(*1) ITRS‘99 ORTC
(*2) 30% off / 3 years improvement
(*3) 30% off / 3 years improvement
February 9,

11. SOC Low Power Premises & Prospects
Technology Node, ASIC Usable Transistors, DRAM capacity, and
Power Supply Voltage conform to ITRS99 ORTC.
Application is not specified, but surely it is high-end SOC
in each generation.
Other premises or prospects are consistent with those of
“SOC Design Productivity”, such as ;
Die size remains around 10mm
Logic gate count ratio continuously decreases from 80%(1999) thru
50%(2002), 35%(2005), into 15%(2011) .
Operation frequency goes up from 150MHz(1999) to 2000MHz(2011) .
February 9,

12. SOC Low Power Assumptions
(cont.)
Assumptions
Power consumption follows a basic well-known formula, that is
Power ∝ C * V * V * f .
“C” can be decomposed into “size factor” and “process factor”.
Total transistor count and technology node represents “size factor”
and “process factor”, respectively.
“V*V” is considered as “voltage factor”, and it is just internal voltage.
Also, “f” is considered as “frequency factor”, and it is just max frequency.
“total power trend” is defined as relative amount of power consumption
for each year(2002, 2005, and 2011) comparing each of above four
“factor” for 1999 as unit(=1).
February 9,

13. SOC Low Power Assumptions(cont.)
“total power trend” is derived by the following calculation,
“total power trend” = “size factor” x “process factor” x
”voltage factor” x “frequency factor”
For “size factor”, constant coefficient 0.85 is applied to Memory
portion, while 1.0 to Logic portion.
Current SOC power consumption is assumed around 3W.
February 9,

14. SOC Low Power Low Power Target A Scenario for solution to keep 3W
(cont.)
Low Power Target
Current power consumption(around 3W) should be kept at the minimum
level.
Ultimate goal is to achieve 0.5W in any technology node generation.
A Scenario for solution to keep 3W
By virtue of a set of potential low power technology, reduction for
each “factor” in the following table is needed to be realized.
2002
2005
2011
Size factor
50%
60%
70%
Process factor
10%
20%
30%
Frequency factor
25%
50%
60%
Voltage factor
17%
33%
40%
February 9,

15. SOC Low Power How to derive “Total Power trend” and “Power estimation”
(cont.)
How to derive “Total Power trend” and
“Power estimation”
Total Power trend
= “size factor” x “process factor” x
”voltage factor” x “frequency factor”
Power estimation (W)
= (Total Power Trend) x 3W
(Ex.) in 2002
Total Power trend
= x 0.72 x 0.64 x 2.67 = 4.84
Hence, Power estimation( W )
= x 3 = W
February 9,

16. SOC Low Power Total Power Trend with No Low Power Solution
(cont.)
Total Power Trend with
No Low Power Solution
Total Power Trend with
Low Power Solution Scenario
to keep 3W
February 9,

17. Low　Power
SOC Low Power
(cont.) W
February 9,

18. Low　Power
SOC Low Power Table
February 9,

19. - Potential Solution Map -
Low　Power
SOC Low Power Design
- Potential Solution Map -
February 9,

20. - Potential Solution Map -
Low　Power
SOC Low Power Design
- Potential Solution Map -
What this figure means ….
Trade-off line between operation frequency and size(Mtr) is put for each
Technology node under the condition to accomplish 0.5W power consumption.
A set of potential low power technology is overlaid in accordance with those
contribution area and degree of range.
Each potential technology is classified into three types( speed, size, and all )
with respect to main contribution.
February 9,

21. DSM Related Issues Overall Premises & Prospects Issues to be examined
Technology Node and Power Supply Voltage conform to ITRS99 ORTC.
Other premises or prospects are consistent with those of
“SOC Design Productivity”, such as ;
Die size remains around 10mm
Operation frequency goes up from 150MHz(1999) to 2000MHz(2011) .
Wiring metal is assumed Al till 2002 and Cu after 2005.
Issues to be examined
Crosstalk noise, RC delay, EMI, IR Drop, and ElectroMigration
For each issue, “estimated value” will be examined in contrast to
“required value” at each Technology node.
February 9,

22. An overall DSM requirements table
(*a) Next Page
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(*b) Next Page
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(*c) Next Page
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(*d) Next Page
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February 9,

23. (*a) (*b) (*c) (*d) An overall DSM requirements table
--- A supplementary explanation ---
(*a)
Derived from 3000 x ( wiring pitch ), and wiring pitch is assumed as 2X of
Technology node. Namely, 1.08 mm is coming from 180nm x 2 x 3000.
At least 3000 wiring pitch parallel interconnect is required.
(*b)
10mm interconnect length is directly coming from that Die size remains 10mm
Obviously, the longest interconnect probably reaches to 10mm under the
above assumption.
(*c)
Source of these values is FCC classB standard( at a distance of 3.0m).
(*d)
Because estimated number of FFs in 2002 is 21, around 20 should be
considered as required number of FFs at each Technology node era.
February 9,

24. DSM
Crosstalk Noise
February 9,

25. - How the the maximal parallel length is calculated -
DSM
- How the the maximal parallel length is calculated -
February 9,

26. DSM
Interconnect Delay
February 9,

27. Electro Magnetic Interference
DSM
Electro Magnetic Interference
February 9,

28. DSM
IR Drop
February 9,

29. Assumed Conditions in table 2-1-4-5
DSM
IR Drop
Assumed Conditions in table
H : Nominal Metal width is assumed as 2X of Technology node.
J : Average power wire length from a pad to Trs. is assumed as 2mm.
K : Nominal power wire width is assumed as 10X of Technology node.
N : Typical gate width(W) is assumed as 10X of Technology node.
Q : Overall average activation ratio is assumed as 5%.
S : Maximum allowable IR drop ratio is defined as 10% of power supply voltage.
V : Average number of clock Trs. driven by one FF is assumed as 4.
February 9,

30. DSM
Electro Migration
February 9,