1. Detector R&D Summary Walter F.J. Müller, GSI, Darmstadt 6 th CBM Collaboration Meeting Piaski, September 7-10, 2005

2. 300 MIMOSA11 @ 1MRad (First results from Frankfurt) 300 Charge collected [ADC] Entries (normalized) 4 pix. 1 pix. Minor degen- eration. Minor degen- eration. Signal remains stable Signal remains stable Shoulder dissapears Signal drops Small peak dissapears MIMOSA11 before and after 1MRad X-rays (@ +10°C, T readout =700µs) Hardened pixel (A0 Sub 1) Standard pixel (A0 Sub 2) Optimal conditions (-25°C, T readout = 170µs) : 15% more noise (~11 e - )=> Chip ok ! Preliminary results and conclusions ! From M. Deveaux

3. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 3 Fast readout speed, the inner layers External 12-bit ADC MIMOSA Offline Cluster finding Output Standard approach for MAPS: Sensor array (~100 pixels/line) ~1000 on - chip ADCs and/or discriminators On - chip cluster- finding processor Output: Cluster information (zero surpressed) The design concept for CBM: Goal: A readout time of  10µs for the CBM 3mm2mm From M. Deveaux

4. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 4 Vertex Detector MAPS  Significant progress in the radiation hardness front  Still much too do, further tests planned demonstrate limit under best operating conditions more tests with neutrons  Fast column-based readout in work since a while building blocks studied chip planned for late next year DEPFET  interesting alternative; 100 um thickness...; puts Λ c in reach  concept for fast readout to be worked out  in an early stage...

5. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 5 Silicon Strip Detector Stations Sectorized segmentation: Basic sensor elements: 200  m thick silicon wafers. double-sided, rad-tolerant. 25  m strip pitch. Inner : 6x4 cm Middle : 6x12 cm Outer :6X20 cm Open questions: strip length, stereo angle (to reduce fake hits) location of read-out (on sensor, all at edge ?) Prosal: Four tracking detector stations, built from a few types of silicon strip wafers. From J. Heuser

6. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 6 Silicon Strip  3 R&D contracts for Sensor, FEE, and layout now active  Many loose ends: module layout  how to arrange and connect sensors into a ladder and to read-out ?  can the read-out be put on the perimeter ? requirements on sensor and read-out  optimal sensor thickness  radiation hardness for read-out

7. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 7 STS technological options ILC, RHIC ILC, Astrophysicis (X-ray observatory) Contact to the Halbleiter Labor of MPI Munich, Peter Fischer (Mannheim) Giga Tracker, LHC upgrade Contact to ALICE group, G. Stefanini, P. Giubellino. ATLAS P. Fischer (other) driving communities: R&D started (talk by M. Merkin) St. Petersburg, Moscow; Obninsk R&D started (next talk) St. Petersburg, Moscow; Obninsk (FNAL), Phenix, Neutron imaging R&D in progress (talk by Michael Deveaux) IReS, (GSI, JWGU) From J. Stroth

8. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 8 Technology development for the PMT FEU-Hive, August 2005 Vladimir Rykalin Technology for the high frequency welding of the covar ring electrodes with the glass tubes has been installed Technology of the Sm evaporation on the PMT window has been tested Technology of bialkaline photocathode activation has been tested The first distributed dinodes have been evaporated, but not still be tested From S. Sadovsky

9. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 9 RICH  GSI-IHEP R&D contract for PMT development now active  Next steps: study and test mirror alternatives (Be, glas, Carbon) Is N radiator feasible ?  Are all properties known ?  Do we need measurements, or simulations ?  Design issues: mirror support  look at existing setups beam pipe  look at the whole system

10. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 10 TRD From C. Garabatos

11. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 11 A preliminary TOF system layout Most central part : highest rate and occupancy Small single cells Intermediate part : high occupancy and large area Single strip shielded RPCs External part : largest area Multistrip (differential) counters The uniformity of the response over the full detector surface is a key element for the physics performance From E. Cordier

12. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 12 RPC  Key issues Rate:  new low resistivity glasses (ceramic, Glaverbel)  high T operation Aging  tested to 600 mC/cm2  much to be learned from HADES/FOPI RPC projects

13. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 13 ECAL  Prototype being build (Y. Kharlov) 20 X 0 ; 0.275 mm Pb+1.5 mm Sci; Target: 3%/sqrt(E) tests on U70 in fall 2005 and 2006  Much emphasis on MC and optimization of layout (I. Korolko) improving e/pi handling hit density  To be resolved: What is the prime mission of ECAL ?  help in e/pi  look for direct photons What is the required solid angle coverage to achieve physics goal

14. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 14 A CBM M-MPW Run CBM organized a Multi-Multi Project Wafer run in UMC 0.18 μm CMOS  6 different parts combined on a 5 x 5 mm 2 wafer  submitted June to Europractice (IMEC)  dies (already cut) just delivered, now come the moments of truth AtkinFischerBrüning DeppeMuthers Tontisirin Content addressable memory 12bit 50MSPS ADC Test structures PreAmp for Si Strip DLL based TDC Clock-Data recovery Coordination: Marcus Dorn @ KIP From W.F.J. Müller

15. 10 September 2005 6th CBM Collaboration Meeting, GSI, September 7-10, 2005 15 CBM FEE/DAQ Demonstrator Mission: Provide a platform to  demonstrate essential architecture elements of the CBM FEE-DAQ concept FEE: self-triggered, data push, conditional RoI based readout CNet: combined data, time, control, and RoI traffic TNet: low jitter clock and synchronization over serial links BNet:high bandwidth, RDMA based architecture E/DCS:integrated approach for DCS/ECS  provide test bed for all future FEE/DAQ prototyping in hardware firmware controlware software  perform beam tests with detector prototypes  form basis for medium-scale applications in intermediate-term experiments Be operational by end 2006  avoid cathedrals, go for the bazaar, try and learn  build a first generation (G1) demonstrator quickly From W.F.J. Müller