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LatchPlanner:Latch Placement Algorithm for Datapath-oriented High-Performance VLSI Design Minsik Cho, Hua Xiang, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri IBM T. J. Watson Research Center, Yorktown Heights, NY 10598 1
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Outline Introduction Preliminaries Latchplanner Complex Datapath Experimental Result 2
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Introduction Such datapath-oriented macros commonly found in high-end VLSI systems (e.g., muxing, buffering, butter-flying, rotating, and so on) propose an automatic latch placement algorithm 3
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Introduction We propose LatchPlanner, which places and fixes latches in a datapath- friendly fashion use dataflow graph to optimize datapath in VLSI designs, in order to optimize overall datapath wirelength and the locations of the key datapath element, latches compare LatchPlanner with the industrially proven and qualitatively golden solutions from a semi-custom methodology,and show that LatchPlanner can be highly effective for datapath-oriented VLSI designs. 4
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Preliminaries Semi-Custom Design Methodology deliver good quality large-scale HW at affordable cost human makes critical design decisions/optimizations manually and leaves the rest of work to tools 5
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Preliminaries Datapath Extraction and Dataflow Graph Datapath extraction is translating regularity/similarity (inherent in datapath) in circuits into mathematical information Once datapaths are identified, a dataflow graph (DFG) can be constructed 6
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Preliminaries DFG is a graph representation of the flow of data through key circuit elements including latches (or flipflops) and pins. The advantage of using DFG is that it captures global view of datapath logic and enables more comprehensive datapath optimization. 7
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LATCHPLANNER 8
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LATCHPLANNER- Latch/Pin Clustering cluster pins and latches separately Clustering is driven by their characteristics, such as physical/logical proximity (based on DFG), instance names Pins are also clustered into ci and co due to their physical separation (e.g., pin locations are known). 9
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LATCHPLANNER- Latch Cluster Sizing and Ordering create a virtual block, Vc, ∀ c ∈ C which will be used to define a physical space where Mc will be placed inside The purpose of sizing is to determine a dimension (wc, hc) of Vc physical certainty :defined as the ratio of the edges to marked nodes in the DFG and the number of objects in a cluster 10
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LATCHPLANNER- Latch Cluster Sizing and Ordering 11
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LATCHPLANNER- Latch Cluster Sizing and Ordering 12
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LATCHPLANNER- Global Latch Placement Global latch placement optimizes two conflicting objectives 1.minimizing datapath wirelength 2.minimizing latch disturbance from input placement 13
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LATCHPLANNER- Global Latch Placement 14
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LATCHPLANNER- Global Latch Placement 15 0 ≤ α ≤ 1
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LATCHPLANNER- Global Latch Placement 16
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LATCHPLANNER- Local Latch Placement local latch placement to minimize the total datapath wirelength of a DFG 17
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Complex Datapath LatchPlanner handles various latch sizes simultaneously Fig. 5 illustrates how LatchPlanner handles complex datapath by optimizing the dimension of each cluster based on Algorithm 1. 18
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Complex Datapath 19 For such cases, we can stack latches accordingly for better datapath- aware placement
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EXPERIMENTAL RESULTS LatchPlanner in C++ performed on a 2.4GHz Linux machine CLP as a LP solver used an in-house placement engine which handles multi-million mixed-size objects and supports the state-of-the-art analytical techniques 20
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EXPERIMENTAL RESULTS 21
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EXPERIMENTAL RESULTS 22 we collected 18 industrial datapath-oriented designs in the 32nm node, and 8 of them (d11–d18) came with manual latch placement data created by highly skilled human designers
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CONCLUSION We propose a novel algorithm, LatchPlanner to optimize datapathoriented design placement We apply LatchPlanner to industrial benchmarks and prove through comprehensive experiments that LatchPlanner is very efficient and effective in handling datapath-oriented designs 23
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