1. Features of the new Alibava firmware: 1. Universal for laboratory use (readout of stand-alone detector via USB interface) and for the telescope readout via Ethernet. 2. Any practical number of ASICs could be addressed. Board operation without ASICs is possible – important for “trigger-only” readout loop for system development. 3. No Microblaze processor core => free of license software. 4. Use 4% of the FPGA resources => room for development. 5. ASIC registers could be read back. 6. Data header is read out => information about pipeline cell. 7. Trigger is vetoed until event is read out. 8. Events are not buffered: high capacity DRAM has no benefits with slow readout and low event frequency. 1

2. MB configuration packet Configuration data stream sent via FT245R IO leads *) 2

3. Command register C = 0x00 – reserved C = 0x01 – set control register C = 0x02 – set threshold DACs C = 0x03 – write / read ASICs C = 0x04 – set delay line C = 0x05 – set latency for Beetle trigger C = 0x06 – reserved C = 0x07 – set Readout Packet length/2 C = 0x08 – set system into event acquisition mode C = 0x09... 0xFF - reserved L = 0 and L = 1 – no operation during write access (!) The valid command has to be specified for L>1 3

4. Setting Control Register Bit 7: reserved Bit 6: reserved Bit 5: fine clock adjustment for ADC Bit 4: fine clock adjustment for ADC Bit 3: enable (1) calibration pulse Bit 2: ext. (0) / automatic (1) reset Bit 1: ext. (0) / 200 Hz int. (1) trigger Bit 0: ext. (0) / 40 MHz int. (1) clock L = 0x03 C = 0x01 (!) External reset = push button / LEMO input Automatic reset = upon event readout D = 0x00 – Beam data taking D = 0x05 – Source data taking D = 0x07 – Pedestal measurements D = 0x0F – Calibration 4

5. Setting Threshold DAC L = 0x26 (38 decimal) C = 0x02 nLD nCS CLK SDI Burr-Brown DAC 7614 5

6. Setting ASICs L = 0x3D (61 decimal) C = 0x03 A4 A3 A2 A1 A0 nWR SCL SDA ROC Beetle V 1.5 6

7. Setting Delay Line L = 0x15 (21 decimal) C = 0x04 AE SC SI Delay line DDD 3D3428 7

8. - disable the trigger - clear event counter - wait for reset pulse upon reset: - wait for the trigger - read ADC_0 (6 + 16 + 128 + 10 words) into RAM 0 - read ADC_1 (6 + 16 + 128 + 10 words) into RAM 1 - read TDC (1 bytes) - read NTC (2 bytes) - ready for the readout - wait for reset pulse Series of actions after writing C = 0x08 L = 0x02 C = 0x08 8

9. LED indicators Green = Trigger = ON, Reset = OFF (indicates Trigger and Reset pulses) Red = R/W access = ON for 100ms (monoflope indicating Bus activity and clock frequency) Push button Event reset, prepare for the next event 9

10. Event Data Format Readout: one ethernet frame (max. payload 1500 bytes) per motherboard per event 10

11. Bit 7: Event ready (digitized after trigger) Bit 6: reserved Bit 5: ASIC 1 ready (160 samples) Bit 4: ASIC 0 ready (160 samples) Bit 3: reserved Bit 2: reserved Bit 1: reserved Bit 0: Read during event processing Status register LSB: phase of DV1 (bits 7..4) and DV0 (bits 3..0) Full event readout could be skipped if the status is erratic 11 MSB :

12. Timing Time between the trigger (leading edge) and every fourth pulse of 40 MHz clock frequency. Purpose: selection of events whose trigger is in phase with switching pipeline. Measurement range: 100ns, resolution: 6 bit (~1.5ns). 12 Time stamps: values of the 5-bit 280 MHz counter latched into register upon time signal (start = trigger, stop = strobe) Stop strobe = 10 MHz, 25% duty cycle

13. 13 Amplitude samples Starts individually for each ASIC after receiving its “Data Valid” response to the trigger. Sampling phase is automatically adjusted, or, if it fails, an error status bit is generated. The sample size is 160 readings (maximum 256), 10 bits each. The content is: - 6 amplitudes for ADC latency, - 16 amplitudes for the ASIC header, - 128 amplitudes for the ASIC channels, - the rest is for the ASIC baseline scan and common mode evaluation.

14. 14 Stand-alone system with USB interface Motherboards (up to 16) integrated into telescope with Ethernet interface Readout options

15. Ethernet frame for the telescope readout “FE MAC” - front-end address “My MAC” - address of the data acquisition PC. For Length < 46, the ethernet packet of 46 bytes (pad) to be sent out or received, but the actual number of bytes exchanged with addressed Motherboard will be as specified by the Length. 15

16. 16 FE MAC convention Packet ID (4 bytes) is useful for search through the DAQ socket buffer. The ID value is taken from the Ethernet packet whose FE MAC address requests data readout (example 02:02:00:00:00:00).