1. Computer Science 516 RISC Architecture: MIPS, ARM

2. How Computer Designs Age Grow or Die Number of instructions enlarges over time Addressing expands to larger memory Control structures grow more complex Interruptions processing Memory mapping Et cetera

3. Growth of Instruction Sets Successful Architectures respond to programmer needs IBM – Move Long to allow movement of 16M characters vs. 256 DEC VAX – CRC instruction for cyclic redundancy check of network messages Intel – Added BOUND instruction to 286 to simplify array index checking Many, many more examples in these and other architectures Thus the name: “Complex Instruction Set Computers” More instructions More complicated instructions, interdependencies, et cetera Costs of CISC More complex instruction decoding Variable length instructions may aggravate this Slower instructions More than one CPU clock sysle to execute an instruction More silicon real estate needed Smaller caches, fewer registers, other limitations

4. Reduced Instruction Set Computers IBM 801 – John Cocke – first paper on RISC concepts - 1976 Several followers Sun, MIPS, Apollo (HP), DEC Alpha, IBM RS6000/Power Design Principles 32-bit words All instructions one word in length Goal: one instruction execution per cycle Generally 32 registers Register file has many more, e.g. 512 Register window identifies which 32 of the 512 are in use This speeds up function calls

5. Comparing Sizes Of Instruction Sets Instruction counts: Pep8: 39 CDC 3300: 200 IBM z/Architecture: 1118 Intel: 1240 (May be low) MIPS: 57 (43 + 14 FP) ARM: 140 (15 Thumb)

6. MIPS Overview Prototypical RISC machine Still produced for cable boxes, consoles, et cetera See CCSF reference or Wikipedia for history

7. ARM Acorn RISC Machine, then Advanced RISC Machines Most-used chipset today (2015) due to phone and tablet use Architecture company, not a chip foundry Design licensed to others Marvell XScale (previously Intel) Apple And over a dozen others A32, A64, “Thumb” implementations

8. Basics: Registers (Arm32) 16 General Purpose registers visible to programmer r0‐r12 general purpose r13 stack pointer r14 link register r15 program counter CPSR current program status register NZCV, mode bits, interrupt mask Setting NZCV bits is optional on a per-instruction basis Register banking Some registers are duplicated for use during interrupt processing

9. ARM Execution States Execution States: affect privileged instructions Needed to run more than one program at once ARM States: User FIQ - fast interrupt IRQ - normal interrupt SVC - service call (program requests, e.g. open a file) Undef - undefined instruction error Abort - memory access errors System - like user but with privileges

10. ARM Instruction Format (32-bit) Extracted from: http://netwinder.osuosl.org/pub/netwinder/docs/arm/ARM7500FEvB_3.pdf

11. ARM Instruction cond Field Each instruction can specify conditions for its execution First four bits of each instruction Tested against NZCV bits in CPSR If test result is zero, instruction not executed This can streamline instruction execution Compare with last week’s Intel jump hint prefix

12. ARM cond Field Values Extracted from: http://netwinder.osuosl.org/pub/netwinder/docs/arm/ARM75 00FEvB_3.pdf

13. Example of ARM cond Field Use For this example, we will show a sequence of ARM assembler instructions with and without use of the cond field to sequence the operations Equivalent code in C++ (assume a, b, and c are ints): if (a < 0) b = a; else b = c;

14. Example of ARM cond Field Use (continued) Without using cond field: LDR R4,a TEQ R4,#0 BPL itsfalse STR R4,b B endif itsfalse: LDR R4,c STR R4,b endif: Using cond field: LDR R4,a TEQ R4,#0 STRMI R4,b LDR R4,c STRPL R4,b

15. ARM Thumb Architecture Changes Problem: ARM 32-bit too large for some uses Embedded controllers with limited memory Solution: “Thumb” variation on standard ARM Cuts some instruction lengths from 32 to 16 bits Allows for two instructions per word If a 16-bit instruction is followed by a 32-bit instruction, assembler inserts No- Operation (NOP) instruction to align the 32-bit instruction to a word boundary Thumb instructions only use the lower 8 or upper 8 of the ARM’s 16 registers Benefit: potentially smaller programs with some loss of performance

16. ARM Extensions 64-bit architecture 32 registers 32 floating point registers Vector Processing feature (NEON) Equivalent to Intel MMX/AVX/et cetera Fewer instructions, of course

17. Some References MIPS Notes from CCSF: http://fog.ccsf.edu/~gboyd/cs270/online/mipsI/mips_basics.html ARM Instruction Reference: http://infocenter.arm.com/help/topic/com.arm.doc.qrc0001l/QRC0001_UAL. pdf UT Austin ARM overview: http://users.ece.utexas.edu/~valvano/EE345M/Arm_EE382N_4.pdf ARM 64-bit overview: http://www.arm.com/files/downloads/ARMv8_Architecture.pdf