1. Lab 4 Report Comments: Procedure Ordering in lab reportProcedure Ordering in lab report report should follow logical flow of what you did in experiment: 1) procedure, 2) results/data, 3) observations… 1) procedure, 2) results/data, observations… etc.report should follow logical flow of what you did in experiment: 1) procedure, 2) results/data, 3) observations… 1) procedure, 2) results/data, observations… etc. Don’t use command style of writing in lab reportsDon’t use command style of writing in lab reports Use engineering notation: MHz, kHz, ms, μs, ns (order of magnitudes of 3)Use engineering notation: MHz, kHz, ms, μs, ns (order of magnitudes of 3) Use some horse sense: stand back and verify your results make sense!Use some horse sense: stand back and verify your results make sense!

2. Lab 4 Comments: The Main Points:The Main Points: –Simulation: allowed you to test a circuit before you actually built the circuitallowed you to test a circuit before you actually built the circuit Simulator was based on device modelsSimulator was based on device models Device models were used to simulate propagation delays in actual devicesDevice models were used to simulate propagation delays in actual devices Static logic hazards were located, tested (they caused glitches), and removed.Static logic hazards were located, tested (they caused glitches), and removed.

3. Lab 5 Comments: The Main Points:The Main Points: –The logic analyzer is a test device that is used to view the signal activity of an actual circuit as opposed to the simulated circuit of Lab 4as opposed to the simulated circuit of Lab 4 –The Xilinx Design Methodology was the steps you took to: 1.model a circuit 2.simulate the model (verify how it will behave) 3.implement a circuit (on the FPGA) with the same output characteristics as the model –Implementing circuits on the FPGA was much easier than wiring the circuit using discrete logic gates (previous experiments).

4. Questions?? Is there such a thing as a 3-input AND gate in an IC?? Do inverters come in IC’s?? How many per package??? Does anyone make a Quad 4-input NAND gate? www.ti.com

5. Combinational Building Blocks: Encoders and Decoders Experiment 6

6. Instructional Objectives: To learn concurrent statements in VHDL.To learn concurrent statements in VHDL. To design combinational building blocks in VHDL and to implement them on the Spartan 3 (Nexys) or Spartan 3E (Nexys 2) FPGA.To design combinational building blocks in VHDL and to implement them on the Spartan 3 (Nexys) or Spartan 3E (Nexys 2) FPGA.

7. VHDL Basics ENTITY – black box description of circuit –declares inputs and outputs, their type, and their size ARCHITECTURE – what’s inside the box –Specifies the implementation of your circuit

8. VHDL Entity ENTITY modulename IS PORT (input1 : IN STD_LOGIC; input2 : IN STD_LOGIC; output1 : OUT STD_LOGIC_VECTOR(0 TO 7); output2 : OUT STD_LOGIC); END modulename;

9. VHDL Architecture ARCHITECTURE myarch OF modulename IS internal signal declarations; BEGIN concurrent statement1; concurrent statement2; concurrent statement3; END myarch;

10. Concurrent Statements: Signal Assignment (<=) ARCHITECTURE my_arch OF module_name IS SIGNAL internal_sig : STD_LOGIC; BEGIN -- a comment begins with two hyphens internal_sig <= input1 AND input2; output1 <= “10101010”; output2 <= internal_sig XOR output1(3); END my_arch;

11. Concurrent Statements: Conditional Signal Assigment ARCHITECTURE myarch OF modulename IS BEGIN output2 <= b WHEN (sel = “01”) ELSE c WHEN (sel = “10”) ELSE d WHEN (sel = “11”) ELSE a; -- default END myarch;

12. Concurrent Statements: Selected Signal Assignment ARCHITECTURE myarch OF modulename IS BEGIN WITH sel SELECT output2 <=b WHEN “01”, c WHEN “10”, d WHEN “11”, a WHEN OTHERS; END myarch;

13. Xilinx CoolRunner CPLD 64 macrocells XCRPlus Development Board

14. 7-Segment LED Displays XCRPlus Development Board Active high Common cathode connected to GND via a transistor a b c d e f g cat1

15. Experiment 6 Overview P1:Design and implement a Binary-Coded-Decimal (BCD) to 7-segment Display Decoder P2: Design and implement an 8:3 Priority Encoder P3:Integrate the circuit from the two previous steps and use the BCD-7seg Decoder to display your output

16. 7-Segment Display Control 1 = V cc 1 COMMON-CATHODE Display CAT1 1-Turn on display 1 0-Turn off display 1 1 = V cc CAT1 AA AB AC AD AE AF AG CAT1 XCRP Board AA 1 cathode

17. 7-Segment Display Control-XCRP The individual LED segments on the 2 displays ARE TIED TOGETHER! So you must use CAT1 and CAT2 to turn ON 1 display and turn OFF the other (or else BOTH will light up with the same pattern. 2 Displays …but only 1 set of segment controls!

18. Nexys Development Board a b c d e f g Four 7-segment LED Displays See Reference Manual (ignore multiplexing)

19. 7-Segment Display Control 1 = V cc 1 0 = Gnd 0 COMMON-CATHODE Display COMMON-ANODE Display (Works like you expect: 1 = ON) Nexys Board: (0 = ON!) So the 7 segment cathode signals (CA..CG) on Nexys Bd are active low

20. CE CF CD CA CG CB CC DP AN0 AN1 AN2 CE CF CD CA CG CB CC DP CA (from FPGA) The individual display segment cathode signals from FPGA (CA..CG and DP) connect to ALL 4 displays at the same time (!!) You must use the common anode signals (AN0..AN3) to turn ON the 1 display you want to use, and turn OFF the rest. Nexys Development Board CB

21. Nexys Development Board Need 1 or 0 (?) from FPGA to Turn ON a Display?? Common anodes (AN0..AN3) connected to Vcc via a transistor Controlled by FPGA outpus 1 0 3.3V

22. Lab Report Comments: VHDL CODE: Use the title banner in all your source code filesUse the title banner in all your source code files

23. -- Company: Cal Poly SLO -- Engineer: Stu Dent & Labpa R. Tner -- -- Create Date: 10-06-07 -- Design Name: BCD-to-7 Segment Decoder -- Component Name: -- Target Device: Digilent Nexys Development Board -- Tool versions: ISE 9.1 -- Description: CPE 169 Experiment #6 – Procedure #1 -- This device converts a single-digit (0-9) 4-bit BCD code to the control -- signals to display the digit on 1 of 4 available 7-seg. displays -- Dependencies: -- Revision: -- 10-13-07: added a few comments (like the instructor said we should!) -- -- Additional Comments: Example VHDL Code Header

24. Lab Report Comments: VHDL CODE: Use the title banner in all your VHDL filesUse the title banner in all your VHDL files Put some comments into your VHDL codePut some comments into your VHDL code Use indents, spacing, skipped lines to make structure obvious and code readable.Use indents, spacing, skipped lines to make structure obvious and code readable. Don’t allow your VHDL code to wrap around between linesDon’t allow your VHDL code to wrap around between lines –examine your outputs before you submit them! Print your VHDL code from Xilinx environment and include with your reportPrint your VHDL code from Xilinx environment and include with your report –don’t put code into the body of the report

25. Lab Report Comments: Circuit Diagrams: –Titled with a descriptive name for the circuit –Brief verbal description of the circuit's function / purpose (what does it do?) –Circuit schematic and/or block diagram Include all input/output signalsInclude all input/output signals –When circuits are implemented in VHDL, signal names on schematics should match signal names used in your VHDL code Show all input/output signal sources / destinations on the Development Board (switches, LEDs, etc.)Show all input/output signal sources / destinations on the Development Board (switches, LEDs, etc.)

26. Lab Report Comments: Timing Diagrams / ModelSim: Title and annotate all timing diagramsTitle and annotate all timing diagrams –and all diagrams for that matter! Show and explain your “Test Vectors”Show and explain your “Test Vectors” –Make clear how you verified proper operation –If not clear, annotate your test input values and results (1’s and 0’s, BCD code,…whatever appropriate format for the signals/vectors.) –Annotate expected outputs where actual outputs displayed Print timing simulations from ModelSim and include with your reportPrint timing simulations from ModelSim and include with your report –Annotated!

27. Test Vectors & Simulation Objective: Verify that each device functions as specified –Thoroughly Verify ALL important functions / behaviors demonstratedALL important functions / behaviors demonstrated ALL output signals operate properlyALL output signals operate properly Common errors / problems shown NOT to occurCommon errors / problems shown NOT to occur –Efficiently Verify Test all possible cases (truth table) only if number of inputs reasonableTest all possible cases (truth table) only if number of inputs reasonable Else, devise more clever subset of test conditions that are “thorough enough”Else, devise more clever subset of test conditions that are “thorough enough”

28. Xilinx Notes Try placing your Xilinx Projects on the remote “H:” drive while you work in lab –Storage on H: drive assigned to your CPE 169 login account –Choose this location when you create your new ISE Project –Default Xilinx directory will be used if you don’t redirect your project file storage when you create the project Goes to C:\Xilinx\... by default

29. Xilinx Notes Try placing your Xilinx Projects on the lab computer “C:” drive while you work in lab –Choose this location when you create your new ISE Project –Default Xilinx directory will be used if you don’t redirect your project file storage when you create the project Goes to C:\Xilinx\... by default Set up your own subdirectory on C: drive C:/Stu_Mary

30. Xilinx Notes Try placing your Xilinx Projects on the lab computer “C:” drive while you work in lab –DO NOT put ISE Projects in folders / directories that have any blank spaces in their names!! Xilinx ISE will have trouble finding the files …and you will get totally FRUSTRATED !!! –Avoid using the “Desktop” Pathname has spaces C:\Documents and Settings\...\Desktop If they’re on C: drive, your files may not be available to you later! –You will need to reuse them for future labs!!! –COPY whole project to your own FlashDrive before leaving

31. DIGITAL ALARM SYSTEM (Experiment #9) TODAY! Next Week Exp 9

32. 1) VHDL source code is used to generate a description of your circuit design. 2) The VHDL source code generated in step 1) is translated into a form which can be used by other software used in the design flow. 3) The Test Bench Waveform software is used to generate signals which are used to verify proper circuit operation in the ModelSim XE simulator. 4) The circuit inputs and outputs are internally “mapped” to FPGA pins which are externally hardwired to input and output devices on the Nexys board. 5) The circuit design is downloaded into the FPGA. 6) Proper operation of the circuit is verified. Xilinx Design Methodology Download to FPGA (ExPort) 1) BE SURE TO PERFORM ALL STEPS IN THE PROPER ORDER TO AVOID PROBLEMS USING THE XILINX TOOLS 2) REFER TO THE DETAILED PROCEDURES IN LAST WEEK’S LAB (Experiment #5) AND THIS WEEK’S LAB (Experiment #6) 3) IF (When!!) YOU ENCOUNTER A PROBLEM, REFER TO #2 ABOVE! - Make sure that you have followed the proper procedures in the proper order before asking (and waiting!) for help.

33. IN CASE YOU DO NOT FINISH The Xilinx and Digilent Tools are all available on-line for FREE Procedure for Downloading them is posted on the CPE-169 Website