1. 3 Objectives Student Name: Ajao Hazzan ID: 073902078 hasanoajao@yahoo.co.uk Kuala Lumpur Infrastructure University Collegehasanoajao@yahoo.co.uk 1 Introductions 4 Methodology and Tools 2.Problem Statements Many semiconductor companies today are facing lots of problems in IC fabrication.These problem are so significant s in determining the success of all semiconductors companies. The problems are yield loss reduction, Failure analysis, Implementation of suitable design of experiment (DOE). Wire Bonding Failure is play major roles in yield loss reduction which relates to packaging yield. Many others have made contributivel effort in solving yield loss problems but not in totality. 7 Future Study 5 Result Analysis 8 Conclusion STUDY AND ANALYSIS OF WIRE BONDWIDTH CONTROL FOR IC DESIGN This project focuses primarily on wire bond control and it explains extensively some of the factors that contributes to yield loss and how it could be controlled so that semiconductor and microelectronics companies can meet their goals and monetary profit plan. The Figure Below show the picture of a device after wire bonding process. The objective of this project is to make known the technical process of wire bonding and some of the factors causing bonding failure. 1.To solve wire bond problems 2.To reduce yield loss related wire bond issue 3.To show the process of IC fabrication. Fabrication Process Figure 4 shows the flow chart of the process it explain the step by step method implemented in solving the wire bond problems. To observe the bond width variation by time series on one particular machine running the Same device and production lot. Parameters setting PowerTimeForceBond Width(Mils) 1 st 2nd1 st 2 nd 1st2 nd 1 st 2nd 95855045554.64.4 958550455554.3 95855045554.24.3 95855045554.2 95855045554.64.2 95855045554.84.2 Ave:4.6Ave:4.4 Delta: 0.2 Mils Parameters Setting PowerTimeForceBond Width(mils) 1 st 2nd1st2nd1 st 2 nd 1st2nd 958045 533.92.6 958045 533.32.7 958045 533.32.5 958045 533.52.8 Ave:3.5Ave:2.65 Delta: 0.85Mils Since the world is heading towards nanotechnology engineers and researchers should begin to look for a better means of providing interconnection in fabrication of these various ICs we have today without using bonding machine. I would suggest by designing the PCB layout of the wire interconnection path and by using photonic wire-laser to provide the interconnection among the various terminals or metallic electron diffusion the interconnection could be made possible for the signal to flow from one point of the device to the other. There are lots of factors which contribute to yield loss and many of it are tied to incurrent or wrongful parameters setup for the machines, bonded surface contaminants, bond geometry, take off angle, loop height, pattern recognition, trend to ceramic, ultimate tensile strength, Increased bond adhesion and pull test results, lower temperature and reduced ultrasonic power, parameters for bond-wire design within the range. If process engineers carefully monitors all these factors mentioned and follows the method proposed in this project wire bond failure and rejects units which reduces most manufacturing companies’ profits and progress will ultimately be reduced. Project Supervisor: Anwar H. Ibrahim Anwar@kliuc.edu.my Project Presenter: Ajao Hazzan ID: 073902078 hasanoajao@yahoo.co.uk Figure 1: K$&S Bonder The Figure 1 below show the Picture of the bonding machine use at the production floor The in Figure 2 is the measuring tool called TM scope, is used for collection of data by measuring the bonding terminals. Figure 2:The TM Scope Figure 3 : Bond Width Spec. Figure 4:The TM Scope The table 1 below show s the good example of what the bond width value range should be. The table 1 Most Important The Graph show s Good Result The table 2 The table 2 below shows an example of poor bondwidth data. The data are below the minimum and maximum specification. The Graph show s Good Result 8 Acknowledgement I really want to thank Freescale semiconductor Malaysia for given me the opportunity to carry out this research work in their company and for all their supports. I am indeed grateful to the management and all my field supervisors. Thanks to you all Figure 4: Pictures at clean room The Figure 1 : Device Picture after wire Bonding