1. ARM Cortex-M0 August 23, 2012 Paul Nickelsberg Orchid Technologies Engineering and Consulting, Inc. www.orchid-tech.com CORTEX-M0 Structure Discussion 3

2. Cortex-M0 Structure Discussion 3 Topics Today CORTEX-M0 Power Management CORTEX-M0 Fault Handling CORTEX-M0 Stack Structures CORTEX-M0 SVC/WFE/WFI Instructions

3. Cortex-M0 Power Management Our discussion focuses on Cortex-M0 Power Management as distinct from additional power management features which may be implemented by a particular device vendor Cortex-M0 Power Management Low Power Instruction Execution Sleep Mode Support Deep Sleep Mode Support Wake-Up Interrupt Controller WFE / WFI Instruction Support Device Specific Power Management Peripheral Power On/Off Control Phase Locked Loop Control Peripheral Clock Source Control Peripheral Clock Rate Control State Saving Registers Real Time Clock Features On-Chip Oscillator Support

4. Cortex-M0 Power Management Low Power Instruction Execution Approx Current in mA Approx Speed in MHz

5. Cortex-M0 Power Management Sleep Mode Stops Processor Clock Deep Sleep Mode Stops System Clock, Power off PLL, and Memory Mode Selection made using SCB Register Cortex-M0 Power Modes

6. Cortex-M0 Power Management WFI Instruction Execution of WFI Instruction causes processor to immediately enter selected sleep mode WFE Instruction Execution of WFE Instruction causes processor to enter selected sleep mode if event bit is set Exit Processor Exception If SLEEPONEXIT bit is set in SCB Register, processor enters selected sleep mode on return from exception to thread mode Cortex-M0 Entry into Power Saving Modes

7. Cortex-M0 Power Management Wake-Up from WFI or SLEEPONEXIT Upon receipt of Prioritized Interrupt, processor immediately resumes execution of instructions Wakeup from WFE Upon receipt of Prioritized Interrupt or external event signal, processor immediately resumes execution of instructions Wakeup using WIC Upon receipt of Wake-up Interrupt Controller Signal, processor immediately resumes execution of instruction. This feature is optional and when implemented usually applies to Deep Sleep wakeup only Cortex-M0 Exit from Power Saving Modes

8. Cortex-M0 Power Management Normal Instruction Execution WFI Normal Instruction Execution Sleep IRQ Time Full Pwr Low Pwr

9. Cortex-M0 Fault Handling HARDFAULT Vector The HARDFAULT Vector catches processor faults Processor Faults SVC Instruction Priority Error BKPT w/o Debugger System Generated Bus Error Attempted execution of instruction in XN Memory Area Attempted execution of undefined instruction Attempted load or store to unaligned address Processor Lockup (Double Fault) Occurs when Fault occurs in NMI or HARDFAULT Handler

10. Cortex-M0 Fault Handling Normal Instruction Execution Bad Instruction Normal Instruction Execution HardFault RESET Bad Instruction Lock Up Reset or NMI restarts processor HardFault Exception preempts all other exceptions

11. Cortex-M0 Stack Structure Cortex-M0 Stack pushes data onto the stack from higher to lower addresses SPContent SP + 0x1CPSR SP + 0x18PC SP + 0x14LR SP + 0x10R12 SP + 0x0CR3 SP + 0x08R2 SP + 0x04R1 SP + 0x00R0 SP Here before Interrupt SP Here after Interrupt

12. Meaning and Implications Processor Architecture – 8 Bit World to 32 Bit World Processing Capability 8 Bit Architecture 32 Bit CORTEX-M0 - Low Power Instruction Execution - Sleep Power Mode - Deep Sleep Power Mode - WFI / WFE Sleep Entry - Fault Handling