1. Improving Op Amp performance
Improving gain
cascoding
cascading
feedback
feed forward
push pull
complementary input
decreasing current
using “analog friendly” CMOS processes
using bipolar

2. Improving speed Increasing UGF,  increase transient speed
Settling may not improve, which depends on PM and secondary poles
Cannot simply increase W/L ratio  optimal sizing for a given CL
Two stage optimal design: can potentially achieve higher UGF than single stage
Increasing PM at UGF,  reduce ringing
Once PM large enough, no effect
Taking care of secondary poles and zeros,  reduce settling time to 1/A0 level
Pole zero cancellation be accurate and at sufficiently high frequency
Cascode or mirror poles sufficiently high frequency
Reduce parasitic capacitances
Increasing current
Using better processes

3. Other specifications to improve
reduced power consumption
low voltage operation
low output impedance (to drive resistive load, or deliver sufficient real power)
large output swing (large signal to noise ratio)
large input common mode range
large CMRR
large PSRR
small offset voltage
improved linearity
low noise operation
common mode stability

4. Two-Stage Cascode Architecture
Why Cascode Op Amps?
Control the frequency behavior
Increase PSRR
Simplifies design
Where is the Cascode Technique Applied?
First stage -
Good noise performance
May require level translation to second stage
Requires Miller compensation
Second stage -
Increases the efficiency of the Miller compensation
Increases PSRR
Folded cascode op amp
Reduce # transistors stacked between Vdd and Vss

5. VDD M4 M2
Vbb
Vin- CL M8 M6 M3 M1
Vin+ M7 M5
Vyy
Vxx M9
Differential
Telescopic
Cascoding
Amplifier
Needs CMFB
On either Vyy
Or VG9

6. Single-ended telescopic cascoding
Analysis very similar to non-cascoded version:
think of the cascode pair as a composite transistor.
M2-MC2 has gm=gm2
go=gds2*gdsC2/gmC2
Ao=gm/go
p1=-go/Co
Right half plane zero: gm/Cgd2

7. Output swing is much less
Vo1 max: VDD – Vsg3-I1*R + |VTP|
Vo1 min: Vicm – Vgs1 – Vbias – VTN
> Vss + Vdssat5 – Vbias – VTN
Several additional pole-zero pairs
At node D2-SC2:
Pole: g=gmC2+gmbC2+gds2+gdsC2
C=CgsC2+cgd2+cdb2
p=-g/C ≈-gmC2/(CgsC2+cgd2+cdb2)
Zero: z≈-gmC2/CgsC2
Pole-zero cancellation at -2pfT of MC2

8. Two stage M4 M4
bias3 M3 M3
bias2
bias1 M2 M2
Vi1 M1 M1
Vi2
CMFB Mb
Depends on supply and first stage biasing, may need level shifting
Analysis very similar, except very small go1, more p/z

9. Cascoding the second stage
Very similar analysis, very small go
Not suitable for low voltage design

10. A balanced version Mirror gain M: gm6:gm4 = gm8:gm3 * gm11:gm10
SR=I6/CL
GB=gm1M/CL
Ao = gm1/go * M
Should have small current in these
But parasitic poles should be high enough

11. Layout of cascode transistors
With double poly:
In a single poly process:

12. Folded cascode
Balanced has better output swing and better gain than telescopic cascode
Both single stage
Neither require compensation
But balanced limits input common mode range due to diode connection
folding

13. Iss determines slew rate
VDD
VDD
folded cascode amp
Same GBW as telescopic 3 4
Iss determines slew rate
Vbb 6 5
Vin+
Vin- CL 1 2 10 11
Iss 9 8
Differential amp requires CMFB

14. I1=I2=Iss/2, I3=I4=Iss*1.2~1.5
Ao=gm1/go; go=gds9*gds11/gm11 + (gds1+gds3)*gds5/gm5;
p1=-go/CL; GB = gm1/CL
Slew rate: Iss/CL
Vomin = Vg11–VTN, Vomax=Vg5+|VTP|
Vicmmin = vs+Vgs1, vicmmax=Vg3+VTN+|VTP|
Power = (Vdd-Vss)*(I3+I4) + biasing power

15. Appropriate Rz moves zero to cancel p2 VDD VDD VDD Triode transistorVb Vb 3 4 15 Vx 5 Cc
vo+
vo1-
Vin+
Vin- 1 2 Rz CL 11 Vy
Iss 13 9 Vb
CMFB
The left side cascode and second stage not shown

16. VDD
VDD
NMOS11b serves as Rz
VDD Vb 3 4 Vb 15
Triode transistor vx 5 Cc
vo+
vo1-
Vin+
Vin- 1 2 CL
11a
Iss Vy
11b 13 Vb 9
CMFB

17. CL
VDD
Vin-
Iss 2 4 5
11b 9 15 13 Cc
vo+
vo1-
CMFB Vb
Vbx
Vby
11a

18. High speed low voltage design
Assume VDD-VSS<VTN-VTP, assume a given Itot
Use minimum length for high speed operation
Use appropriate Von13,15 to achieve balance between high fT and high swing
Select Von4,5,9,11 so that vo1 has + – 10% (VDD-VSS) swing
Set desired vocm at (VDD+VSS+Vdssat13-Vsdsat15)/2
Size transistors so that Vgs13 = mid range of vo1 swing

19. Show that the compensation scheme has very similar pole splitting effect as in 7 transistor op amp before
Show that appropriate sizing of M11b can cause the zero to move over p2
If CMFB is applied at G3,4, compensation can be connected to channel of M9
Show that with an appropriate attenuator, the go at vo1 can be made zero by positive feedback from opposite side vo1+ to G5
Show that with an appropriate gm5, the go at vo1 can be made zero by positive feedback from opposite side vD12 to G5

20. PUSH-PULL Output Stagev v
At low frequency, vg7 and vg8 nearly constant as vo swings

21. PUSH-PULL Output Stage
Let AI be the current gain from M1 to M7
Icc=sCcVg6, (Iss-Icc)/2–>I3, DI7=AI*Icc/2
KCL at D6: -Icc + Vg6*gm6 +DI7=0, 
Can choose AI so that z cancels p2 for high speed

22. PUSH-PULL Output Stage

23. Problem: bias current in second stage unknown
True push pull
VDD
VDD
VDD 3 4 5
Vin+
Vin- CL 1 2
Iss 6
Problem: bias current in second stage unknown

24. If VDD-VSS is sufficient3 4 5
Vbn
Vbp CL
Vin+
Vin- 1 2 6
But gain of 1st stage reduced!
Iss

25. To recover gain:
VDD
VDD
VDD
VDD 3 4 5
Vbp
Vbn CL
Vin+
Vin- 1 2 6
Iss

26. VDD
Vin+ CL
Vin-
Iss 1 2 3 4 5 6
Vbp
Vbn

27. Figure 7.11 in book: process variations can cause large change in M21/22 current, and mismatch in M21 vs M22 bias results in offset voltage

28. Same comment applies to this one
Figure 7.1-2
Same comment applies to this one
Both can have very small quiescent current when vin≈0
But provide large charging or discharging current
power efficiency

29. Dynamically Biased (Switched) Amplifiers
Switched amplifiers lead to smaller parasitic capacitors and therefore higher frequency response.
Switched amplifiers require a non-overlapping clock
Switched amplifiers only work during a portion of a clock period
Bias conditions are setup on one clock phase and then maintained by capacitance on the active phase
Switched amplifiers use switches and capacitors resulting in feed-through problems
Simplified circuits on the active phase minimize the parasitics

30. Dynamically Biased Amplifiers
Two phase non-overlapping clocks

31. Dynamically Biased Inverter
In f2 offset and bias are sampled
In f1, COS provides offset cancellation plus bias for M1; CB provides the bias for M2.

32. Dynamic, Push-pull, Cascode Op Amp

33. VDD - VB2 - vIN
vIN - VSS - VB1

34. A Dynamic Op Amp which Operates on Both Clock Phases
True push-pull
Single stage
Differential-in
Single-ended out
No tail current
Off-set cancelled
For large swing:
Remove cascodes
S. Masuda, et. al.,
1984

35. LOW VOLTAGE OP AMPS We will cover: Methodology:
Low voltage input stages
Low voltage bias circuits
Low voltage op amps
Examples
Methodology:
Modify standard circuit blocks for reduced power supply voltage
Explore new circuits suitable for low voltage design

36. ITRS Projection – near term

37. ITRS Projection – longer term

38. Low-Voltage, Strong-Inversion Operation
Reduced power supply means decreased dynamic range
Nonlinearity will increase because the transistor is working close to VDS(sat)
Large values of λ because the transistor is working close to VDS(sat)
Increased drain-bulk and source-bulk capacitances because they are less reverse biased.
Large values of currents and W/L ratios to get high transconductance
Small values of currents and large values of W/L will give smallVDS(sat)
Severely reduced input common mode range
Switches will require charge pumps

39. Input common mode range drop
VDD – VDS3sat + VT1 > vicm > VDS5sat + VT1 + VEB1
> vicm >

40. p-n complementary input pairs
n-channel: vicm > VDSN5sat + VTN1 + VEBN1
p-channel: vicm <VDD- VDSP5sat - VTP1 - VEBP1

41. Non-constant input gm

42. constant input gm solution

43. Set VB1 = Vonn and VB2 = Vonp

44. Rail-to-rail constant gm input

45. Rail-to-rail constant gm input
Coban and Allen, 1995

46. The composite transistor

48. Bulk-Driven MOSFET

49. Bulk-Driven, n-channel Differential Amplifier
I1=I2=I5/2
As Vic varies, Vd5 changes and gmb varies 
Varied gain, slew rate, gain bandwidth; nonlinearity; and difficulty in compensation

50. Bulk-driven current mirrors
Increased vin range and vout range

51. Traditional techniques for wide input and output voltage swings
Iin+Ib Ib Ib
Iin
VT+2Von
>2Von
1/4 1 + 1
VT+Von
Von –
Von
VT+Von 1 1

52. Traditional techniques for wide input and output voltage swings
Iin
Iin Ib Ib +
VT+2Von Io
Veb
>2Von –
1/4 1
Von
Von
VT+Von 1 1

53. A 1-Volt, Two-Stage Op Amp
Uses a bulk-driven differential input pair,
wide swing current mirror load, and emitter follower level shifter

54. Low voltage VBE and PTAT reference

55. Low voltage band-gap reference
Needs a low voltage op amp
Vref=I3*R3=

56. One example implementation

57. Threshold Voltage Tuning for low power supply voltages operation

58. Implementation of the voltage sources

59. A low voltage Op Amp core

60. Op Amp Implementation Clock booster Bias voltage generator
Leakage from M3 make less than 2VDD, two stages are used.
R is used for
Clock booster
Bias voltage generator

61. Clock booster (doubler)
CB1 >> CBL

62. Experimental Results Power supply 750mV Slew Rate 3.1V/uS GB 3.2MHz
DC gain
62dB
Input offset voltage
2.2mV
Input common mode range
0.1V-0.58V
Output swing for linear operation
0.31V-0.58V
PSRR at DC
82dB
CMRR at DC
56dB
Total power consumption
38.3uW
Power supply range……
Offset voltage
package

63. Regulated Cascode Vb7 Vb5 VG2 A3 A4 VG3 A1 A2 Q7 Q8 Q11 Q2 Q1 Vi- Vi+

64. Regulated Cascode: one realizationk VD VS

65. Common mode feedback for low voltage

66. 1.5v op amp for 13bit 60 MHz ADC

67. Output Stage and CMFB

68. Folded cascode with AB output
Lotfi 2002

69. Simulated performance
0.25 um process
1.5 V power supply
82 dB DC gain
2 V p-p diff output swing
170 MHz 10 pF load
77o PM with b = 1/5
0.02% 1V step settling time: 8.5 ns
Full output swing Op Amp power: 25 mW

70. Differential difference input AB output
Alzaher 2002

71. Nested Miller Cap Amplifier
Not much successes

72. Low voltage amp

73. Low voltage amp

74. LOW POWER OP AMPS Op Amp Power = (VDD-VSS)*Ibias
Reduce supply voltage: effect is small
Many challenges in low voltage design same as before
Reduce bias: factor of hundred reduction
Weak inversion operation
Nano-amp to small micro-amp currents
Needs small current biasing circuits and small current reference generators
Needs output stage to drive the load
Design it so that it consume tiny quiescent power
But generate sufficient current for large signals
Tradeoff speed for reduced power

75. Sub-threshold Operation
Most micro-power op amps use transistors in the sub-threshold region.
np~1.5; nn~2.5

76. Two-Stage, Miller Op Amp in Weak Inversion
At VDD-VSS=3V, ID5=0.2uA, ID7=0.5uA, got A=92dB, GB=50KHz, P=2.1uW

77. Push-Pull Output in Weak Inversion
First stage gain
Total gain
S=W/L

78. Increasing gain What is VON? L5=L12, W12=W5/2 S13<<S4 go
Gain=gm/go

79. Increasing Iout with positive feedback
When vi1>vi2
i2>i1
i26=i2-i1>0
i27=0
i28=A*i26
itail=i5+i28
=i1+i2
i2/i1=e(vi1-vi2)/nvt
=evin/nvt
i2=i1evin/nvt
i1=I5 /{A+1-(A-1)evin/nvt)}

80. A=0 is normal case
A > 0 can greatly
enhance available
output current
for load driving

81. i1+i2 much faster than i2-i1
as vin 
New i1+i2
i2=i1evin/nvt
i1=i2
A=3 I5
i1+i2=I5
A=2
A=1
A=0 I5 i2