1. Chapter 5 Computer Organization

2. Distinguish between the three components of a computer hardware. List the functionality of each component. Understand memory addressing and calculate the number of bytes for a specified purpose. After reading this chapter, the reader should be able to: O BJECTIVES Distinguish between different types of memories. Understand how each input/output device works. Continued on the next slide

3. Understand the systems used to connect different components together. Understand the addressing system for input/output devices. Understand the program execution and machine cycles. O BJECTIVES (continued) Distinguish between programmed I/O, interrupt-driven I/O and direct memory access (DMA). Understand the two major architectures used to define the instruction sets of a computer: CISC and RISC.

4. Figure 5-1 Computer hardware (subsystems)

5. CENTRALPROCESSING UNIT (CPU) CENTRALPROCESSING 5.1

6. Figure 5-2 CPU

7. MAIN MEMORY 5.2

8. Table 5.1 Memory units Unit Unit ------------ kilobyte megabyte gigabyte terabyte petabyte exabyte Exact Number of bytes Exact Number of bytes ------------------------ 2 10 bytes 2 20 bytes 2 30 bytes 2 40 bytes 2 50 bytes 2 60 bytes Approximation Approximation ------------ 10 3 bytes 10 6 bytes 10 9 bytes 10 12 bytes 10 15 bytes 10 18 bytes

9. Figure 5-3 Main memory

10. Memory addresses are defined using unsigned binary integers. Note:

11. Example 1 A computer has 32 MB (megabytes) of memory. How many bits are needed to address any single byte in memory? Solution The memory address space is 32 MB, or 2 25 (2 5 x 2 20 ). This means you need log 2 2 25 or 25 bits, to address each byte.

12. Example 2 A computer has 128 MB of memory. Each word in this computer is 8 bytes. How many bits are needed to address any single word in memory? Solution The memory address space is 128 MB, which means 2 27. However, each word is 8 (2 3 ) bytes, which means that you have 2 24 words. This means you need log 2 2 24 or 24 bits, to address each word.

13. Figure 5-4 Memory hierarchy

14. Figure 5-5 Cache

15. INPUT / OUTPUT 5.3

16. Figure 5-6 Physical layout of a magnetic disk

17. Figure 5-7 Surface organization of a disk

18. Figure 5-8 Mechanical configuration of a tape

19. Figure 5-9 Surface organization of a tape

20. Figure 5-10 Creation and use of CD-ROM

21. Table 5.2 CD-ROM speeds Speed ------------ 1x 2x 4x 6x 8x 12x 16x 24x 32x 40x Data Rate Data Rate ------------------------ 153,600 bytes per second 307,200 bytes per second 614,400 bytes per second 921,600 bytes per second 1,228,800 bytes per second 1,843,200 bytes per second 2,457,600 bytes per second 3,688,400 bytes per second 4,915,200 bytes per second 6,144,000 bytes per second Approximation Approximation ------------ 150 KB/s 300 KB/s 600 KB/s 900 KB/s 1.2 MB/s 1.8 MB/s 2.4 MB/s 3.6 MB/s 4.8 MB/s 6 MB/s

22. Figure 5-11 CD-ROM format Using correction code hamming code

23. Figure 5-12 Making a CD-R

24. Figure 5-13 Making a CD-RW transparent SIAT silver

25. Table 5.3 DVD capacities Feature Feature --------------------------------- single-sided, single-layer single-sided, dual-layer double-sided, single-layer double-sided, dual-layer Capacity Capacity ------------ 4.7 GB 8.5 GB 9.4 GB 17 GB

26. SUBSYSTEMINTERCONNECTIONSUBSYSTEMINTERCONNECTION 5.4

27. Figure 5-14 Connecting CPU and memory using three buses

28. Figure 5-15 Connecting I/O devices to the buses

29. Figure 5-16 SCSI controller

30. Figure 5-17 FireWire controller High speed device 50 Mb/s

31. Figure 5-18 USB controller Low speed device 1.5 Mb/s

32. Figure 5-19 Isolated I/O addressing Instruction used to R/W memory is different from that used I/O devices

33. Figure 5-20 Memory-mapped I/O addressing Cpu treats each register in the controller as a word in memory. Smaller no. of instruction, read add, if the address is for memory, data will be red from memory, if it’s for a register it will red from register.

34. PROGRAMEXECUTIONPROGRAMEXECUTION 5.5

35. Figure 5-21 Steps of a cycle

36. Figure 5-22 Contents of memory and register before execution

37. Figure 5-23.a Contents of memory and registers after each cycle

38. Figure 5-23.b Contents of memory and registers after each cycle

39. Figure 5-23.c Contents of memory and registers after each cycle

40. Figure 5-23.d Contents of memory and registers after each cycle

41. Synchronization During transfer of data from I/O to CPU Because I/O devices are much slower than CPU Three methods can be used for this synchronization. 1.Programmed I/O 2.Interrupt-driven I/O 3.DMA

42. Figure 5-24 Programmed I/O

43. Figure 5-25 Interrupt-driven I/O

44. Figure 5-26 DMA connection to the general bus

45. Figure 5-27 DMA input/output