1. Pipeline Data Hazards Warning, warning, warning! Read 4.8 Peer Instruction Lecture Materials for Computer Architecture by Dr. Leo Porter is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License. Dr. Leo Porter Creative Commons Attribution-NonCommercial-ShareAlike 3.0 Unported License

2. Pipelining Key Points Pipeline processors aim at improving instruction throughput. Control signals are generated by combinational logic and passed with the instruction ET=IC*CPI*CT

3. Dealing With Data Hazards In Software – In Hardware – Data Hazards are caused by instruction dependences. For example, the add is data-dependent on the subtract: subi $5, $4, #45 add $8, $5, $2 Data Hazards are caused by instruction dependences. For example, the add is data-dependent on the subtract: subi $5, $4, #45 add $8, $5, $2 nops/independent insts Pipeline stalls Forwarding

4. Pipeline Stalls To insure proper pipeline execution in light of register dependences, we must: –detect the hazard –stall the pipeline

5. Detecting the Hazard IMReg ALU DMReg IMReg ALU DM IMReg ALU DMRegIMReg ALU DMRegIMReg ALU DMReg CC1CC2CC3CC4CC5CC6CC7CC8 6 types of data hazards –two reg reads * 3 reg writes Draw arrows from 3 previous instructions Jump ahead two slides To show the comparison logic

6. Once you detect the hazard in ID – what must you do to insert the nop and “stall”? 1.Flush all instructions in the pipeline (set control signals to 0). 2.Set all control signals going to ID/EX register to zero. 3.Set PCWrite to zero. 4.Set IF/ID register write to zero. Stalling the pipeline SelectionChanges A1, 3, 4 B1, 2, 3 C2, 3, 4 D1 ENone of the above

7. The Pipeline Show comparison logic, go back 1 slide, then show how to stall

8. What else can we do other than just stalling? Registers ID/EX ALU EX/MEMMEM/WB Data Memory 0101 IMReg ALU DMRegIMReg ALU DMReg add $2, $3, $4 add $5, $3, $2 Show how the value is already available

9. Reducing Data Hazards Through Forwarding EX Hazard: if (EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRs)) ForwardA = 10 if (EX/MEM.RegWrite and (EX/MEM.RegisterRd != 0) and (EX/MEM.RegisterRd = ID/EX.RegisterRt)) ForwardB = 10 (similar for the MEM stage) Point out source registers being pass along Show how the logic applies.

10. Data Forwarding The Previous Data Path handles two types of data hazards –EX hazard –MEM hazard We assume the register file handles the third (WB hazard) –“Register File forwarding” –If the register file is asked to read and write the same register in the same cycle, we assume that the reg file allows the write data to be forwarded to the output –We’re still going to call that forwarding. Point out that although the book talks about writing on the neg edge and always reading, this isn’t accurate for today. Today – forwarding in the regfile is explicit.

11. Eliminating Data Hazards via Forwarding IMReg ALU DMReg IMReg ALU DM IMReg ALU DMRegIMReg ALU DMRegIMReg ALU DMReg CC1CC2CC3CC4CC5CC6CC7CC8 sub $2, $1, $3 and $6, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Draw the arrows for the add, or, and add instructions.

12. Forwarding in Action add $1, $12, $3sub $12, $3, $4add $3, $10, $11Memory AccessWrite Back

13. Forwarding in Action Instruction Fetchadd $1, $12, $3sub $12, $3, $4add $3, $10, $11Write Back

14. Eliminating Data Hazards via Forwarding?? CC1CC2CC3CC4CC5CC6CC7CC8 lw $2, 10($1) and $12, $2, $5 or $13, $6, $2 add $14, $2, $2 sw $15, 100($2) Do this on our own

15. How many stalls occur and how many values require hardware forwarding support to avoid stalling for our MIPS 5-stage pipeline. add $3, $2, $1 lw $4, 100($3) and $6, $4, $3 sub $7, $6, $2 add $9, $3, $6 SelectionStallsForwarded values A13 B24 C23 D15 ENone of the above

16. Datapath Combined Point out this logic now just checks to see if the next instruction reads from mem Seque – we know MIPS – but can we apply these principles to other pipelines

17. Suppose EX is the longest (in time) pipeline stage. To reduce CT, we split it in half. Given the following pipeline: IF ID EX1 EX2 M WB Assume the input data must be available at the start of EX1 and the output is available after EX2.How many hardware stalls would be required in the following code (assuming hardware forwarding wherever possible)? lw r1, 0(r3) add r2, r1, r3 SelectionNumber of stalls A0 B1 C2 D3 E4

18. Suppose EX is the longest (in time) pipeline stage. To reduce CT, we split it in half. Given the following pipeline: IF ID EX1 EX2 M WB Assume the input data must be available at the start of EX1 and the output is available after EX2. How How many hardware stalls would be required in the following code (assuming hardware forwarding wherever possible)? add r1, r2, r3 add r4, r1, r3 SelectionNumber of stalls A0 B1 C2 D3 E4

19. Suppose IF and M are the longest stages. To reduce CT, we split each in half. Given the following pipeline: IF1 IF2 ID EX M1 M2 WB Assume the input data must be available at the start of F1/M11 and the output is available after F2/M2. How many hardware stalls would be required in the following code (assuming hardware forwarding wherever possible)? lw r1, r2, r3 sw r1, 0 (r3) SelectionNumber of stalls A0 B1 C2 D3 E4

20. As an ISA designer - you have a choice between dealing with these hazards in software or hardware. Which might you choose and why? SelectionHW or SWWhy? (Best answer) ASoftwareCompilers have a large window of instructions available to do reordering to eliminate hazards BSoftwareDetecting data hazards in hardware can be difficult and expensive CHardwareHardware knows at runtime the actual dependencies and can exploit that knowledge for better reordering DHardwareExposing the number of required stalls violates the abstraction between hardware and software ESoftwareFor different reasons than above Dealing with Data Hazards All these are reasonable – but reason D is the driving factor for hardware dealing with hazards (be sure to highlight no single right answer). Highlight a full discussion of this is in graduate architecture, but we’ll touch on it some later

21. Data Hazard Key Points Pipelining provides high throughput, but does not handle data dependences easily. Data dependences cause data hazards. Data hazards can be solved by: –software (nops) –hardware stalling –hardware forwarding Our processor, and indeed all modern processors, use a combination of forwarding and stalling. ET = IC * CPI * CT