1. The ARM7TDMI Processor Block Diagram Vector Table
Exception Priorities and Interrupts
JTAG Interface

2. The ARM7TDMI ARM7TDMI Core
mclk
wait*
eclk
bigend
irq*
fiq*
isync
reset*
enin*
enout*
enouti*
abe
ale
ape
dbe
tbe
busen
highz
busdis
ecapclk
dbgrq
breakpt
dbgack
exec*
extern1
extern0
dbgen
rangeout0
rangeout1
dbgrqi
commrx
commtx
opc*
cpi*
cpa
cpb
Vdd
Vss
ARM7TDMI
Core
A[31:0]
Din[31:0]
Dou[31:0]
D[31:0]
bl[3:0]
r*/w
mas[1:0]
mreq*
seq
lock
trans*
mode*[4:0]
abort
Tbit
tapsm[3:0]
ir[3:0]
tdoen*
tck1
tck2
screg[3:0]
drivebs
ecapclkbs
icapclkbs
highz*
pclkbs
rstclkbs
sdinbs
sdoutbs
shclkbs
shclk2bs
TRST*
TCK
TMS
TDI
TDO
Clock Control
Configuration
Interrupts
Clock Control
Initialization
Configuration
Bus Control
Interrupts
Initialization
Thumb mode is supported in Hardware, but not supported in all BSPs.
For more information about the ARM core, we suggest reading ARM system-on-chip Architecture by Steve Furber (ISBN ).
Debug
Boundary Scan Extensions
Coprocessor Interface
JTAG Controls
Power

3. The ARM Vector table The ARM Vector Table 32-bit Memory Space Address
0xFFFF FFFF
32-bit
Memory
Space
Address
Vector 0x
RESET 0x
Undefined Instruction 0x
SWI Software Interrupt
0x C
Abort (Prefetch) Bus Error Inst Fetch 0x
Abort (Data) Bus Error Data Fetch 0x
Reserved (not used) 0x
IRQ Interrupt
0x C
FIQ Interrupt 0x

4. Exception Priorities Highest Priority Lowest Priority Reset Data Abort
FIQ
IRQ
Prefetch Abort
Undefined, SWI
Lowest Priority
NOTES:
Data Abort, Prefetch Abort, and Undefined Represent Unexpected and Erroneous Software Operation.
IRQ is most common exception during run-time.

5. IRQ and FIQ Interrupts Net+ARM ASIC Gen Module ARM7TDMI Core BBus
NOTES:
There is no direct external access to either IRQ of FIQ.
FIQ can occur while FIRQ is being processed.

6. JTAG Debugger Interface
ARM7TDMI Core
TRST*
TCK
TMS
TDI
TDO
BBus
Net+ARM ASIC