1. © 2000 Altera Corporation 1 Designing with Quartus

2. © 2000 Altera Corporation 2 Quartus Development System Feature Overview

3. © 2000 Altera Corporation Quartus Development System Quartus Development System features: –Fully integrated design entry, processing, and verification tools: Multiple design entry methods Logic synthesis Place & route Simulation Timing analysis Device programming –NativeLink –Revision Control Interface –Intellectual Property (IP) Support –SignalTap –Extensive On-Line Help

4. © 2000 Altera Corporation 4 More Features Incremental Recompilation Internet-enabled technical support Supports multiple platforms 1 –Quartus runs on Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations Extensive on-line help Network licensing supported on both Windows-based PCs and Unix-based workstations Note 1: Please refer to Quartus’ ReadMe file to determine which version of the Operating System is supported for each platform

5. © 2000 Altera Corporation 5 Quartus Operating Environment Project Navigator Window Messages Window Status Window

6. © 2000 Altera Corporation 6 Quartus Design Methodology

7. © 2000 Altera Corporation 7 System Production Design Specification Design Compilation Functional Verification Timing Verification Device Programming In-System Verification Design Modification Design Entry Command-Line Mode: Scripting

8. © 2000 Altera Corporation 8 Design Methodologies Quartus supports three common design methodologies: –Top-down Create a top-level of the design first, and then break down the design into lower-level design blocks. –Bottom-up Begin by creating the lower-level design blocks first and then stitch together the design at the top-level. –Middle-out Start in-between Top-down and Bottom-up design methodologies

9. © 2000 Altera Corporation 9 Design Entry Multiple design entry methods –Quartus Block/Schematic Editor Text Editor –AHDL, VHDL, Verilog Memory Editor –Hex, Mif –Third party EDA tools EDIF HDL VQM –Add flexibility and optimization to the design entry process by: Mixing and matching design files Using LPM and Megafunctions to accelerate design entry

10. © 2000 Altera Corporation 10 Quartus Memory Editor Quartus Text Editor Quartus Block Editor Top- Level File.bdf.gdf Top-level design files can be.bdf,.tdf,.vhd,.vhdl,.v,.vlg,.edif or.edf.bsf.vhd Block File Symbol File Text File Text File.v.v Text File Imported from third- party EDA tools Exemplar, Synopsys, Synplicity, etc... Generated within Quartus VHDL Schematic.tdf Text File AHDLVerilog.edf.edif Text File.v,.vlg,.vhd,.vhdl, vqm MegaWizard Manager Design Entry Files

11. © 2000 Altera Corporation 11 Resource Libraries The following libraries are added to the project by default –LPM Library of Parameterized Modules ( LPMs ) Industry standard logic functions –LPM_ADD_SUB, LPM_COUNTER, etc. –Others 7400 series logic functions (to provide support for older designs) Other legacy functions like 161mux, 8fadd, etc. –Primitives Basic logic building blocks

12. © 2000 Altera Corporation 12 Step 1: Select User Libraries Step 2: Select Library path Step 3: Click Add Step 4: Click OK Adding User Libraries can also be done using Project Wizard. Refer to the section on Project Wizard for more information Add User Libraries Menu Bar: Project > General Setting...

13. © 2000 Altera Corporation 13 Text Design Entry Available Features –Line numbering in the HDL text files –Preview of HDL templates –Syntax Coloring –When editing a text file, an asterisk (*) appears next to the filename After saving the file, the asterisk disappears Enter text description –AHDL (.tdf) –VHDL (.vhd) –Verilog (.v)

14. © 2000 Altera Corporation 14 HDL Templates Menu Bar: Insert > Template… or click on the shortcut button Select HDL language. Select Template section. Preview window display section

15. © 2000 Altera Corporation 15 Upper Left-hand Corner of the Screen Edit Options Find Matching Delimiter Upper Left-hand Corner of the Screen Increase Indent Decrease Indent

16. © 2000 Altera Corporation 16 Text Editor: Options Menu Bar: Tools > Options...

17. © 2000 Altera Corporation 17 AHDL Altera Hardware Description Language High-level hardware behavior description language Uses Boolean equations, arithmetic operators, truth tables, conditional statements, etc. Can create AHDL Design File (.tdf) with the Quartus text editor or any standard text editor and compile it directly with Quartus Text editor has AHDL templates and syntax coloring

18. © 2000 Altera Corporation 18 Learn more about Verilog in Altera Verilog Customer Training Classes Verilog 1993 Verilog IEEE 1364 standard Hardware Description Language Can create Verilog design files with the Quartus text editor or any standard text editor and compile it directly with Quartus Text editor has Verilog templates and syntax coloring Features –Tasks –2-D Arrays –Empty placeholder –State machine recognition –Verilog TestBench support

19. © 2000 Altera Corporation 19 Learn more about VHDL in Altera VHDL Customer Training Classes VHDL VHSIC Hardware Description Language 1987 and 1993 IEEE 1074 standards supported Can create VHDL design files (.vhd) with the Quartus text editor or any standard text editor and compile it directly with Quartus Text editor has VHDL Templates and syntax coloring VHDL TestBench support

20. © 2000 Altera Corporation 20 Block Diagram/Schematic File Editor This is both a block diagram editor and a schematic file editor Block diagram entry is mainly for top-down design methodology Schematic file entry is the traditional schematic design entry User can enter blocks, primitives, LPMs, and megafunctions from Quartus-provided or user libraries Provides “smart” block connection and mapping

21. © 2000 Altera Corporation 21 Block Editor - Entry Process Create new block design file –Draw block diagram or enter design components (symbols) –Enter port and parameter information –Connect components with connectors (wires, buses & conduits) –Add mapping properties to conduits, if needed Save the design –The file extension is.bdf Generate HDL/graphic file for the lower-level blocks Create symbol or include file of the top-level block design

22. © 2000 Altera Corporation 22 Open new file Select Block/Schematic Document Block Editor - Create New File Create a block/schematic file Menu Bar: File > New > Block/Schematic document

23. © 2000 Altera Corporation 23 Block Editor - Enter Symbols Symbol libraries Click on the toolbar option “Insert Symbol” OR Double-click in block editor to insert symbols Preview the Symbol Enter symbols from libraries - LPMs, primitives, others

24. © 2000 Altera Corporation 24 Right-click on the block. Select Properties from the pop-up menu. Enter port information. Click on the toolbar option “Block” to draw a block diagram Block Editor - Draw Block Create block using the toolbar and enter ports Block A

25. © 2000 Altera Corporation 25 Block Editor - Make Connections Wire Bus Wire (Single bit line) Bus (Multiple bits) Conduit –Connects blocks to any other objects

26. © 2000 Altera Corporation 26 Block Editor - Check Conduit Connections Right Mouse Click on the connector > Conduit Properties

27. © 2000 Altera Corporation 27 MapperConnector Block Editor - “Smart” Connections Quartus has “smart” block connecting and mapping –Unnecessary to label conduits if the I/O names between different blocks are the same –One conduit will connect all the common I/Os between the blocks Block ABlock B

28. © 2000 Altera Corporation 28 Block Editor - Conduit Properties Map the block I/Os when the I/O names are different between the blocks 1 First, label the connector Select connector  right-click  choose Properties  enter Name Block B ConnectorAB Enter Signal Block A

29. © 2000 Altera Corporation 29 Double-click on the mapper ConnectorAB Block B Mapper Properties 2 Select the mapper and double-click on it to open the Mapper Properties dialog box 3 In the General tab, set the Mapper Type - Input, Output, Bidir 4 In the Mappings tab, set the I/O on block and connector signal 5 Click Add and hit OK Block A

30. © 2000 Altera Corporation 30 Mapper Annotation Box Block Editor - Make Connections 6 Enter mapper properties on both the blocks 7 Now, the I/Os are connected Block A ConnectorAB Block B IIIII

31. © 2000 Altera Corporation 31 Block Editor - Save Design Save the design file with.bdf extension Design File Name Block A ConnectorABBlock B

32. © 2000 Altera Corporation 32 Block Editor - Generate Design File Create HDL or graphic design file for individual blocks Right-click on the symbol to open the pop-up menu Select Create Design File from the menu Block A ConnectorAB Block B

33. © 2000 Altera Corporation 33 Block Editor - Generate Design File Choose from the File Type and enter File Name Select from AHDL, VHDL, Verilog or Graphic option Block A ConnectorAB Block B

34. © 2000 Altera Corporation 34 Create Design File module myblk ( // {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE! in1, in2, out1, out2 // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE! ); // Port Declaration // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! input in1; input in2; output out1; output out2; // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! endmodule These lines are necessary for Quartus to update the source code Quartus creates a design file that contains the port names that are specified in your block.

35. © 2000 Altera Corporation 35 Update Design File... Right mouse click Update Design File... If you change the name or number of I/Os in your block, Quartus can update the design file for you Before After

36. © 2000 Altera Corporation 36 Updated Design File module myblk ( // {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE! in1, in2, out1, out2, out3 // {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE! ); // Port Declaration // {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! input in1; input in2; output out1; output out2; output out3; // {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! endmodule Quartus updated the source file with the additional pin, out3

37. © 2000 Altera Corporation 37 Menu Bar: Tools > Create Symbol for Current File Menu Bar: Tools > Create Include File for Current File Block Editor - Designing Hierarchically? Creates.bsf file Creates.inc file

38. © 2000 Altera Corporation 38 Menu Bar: Tools > Options Block Editor - Options

39. © 2000 Altera Corporation 39 Memory Editor Create or edit memory files in hex format (.hex) or memory initialization format (.mif) For Design Entry –If you have a memory block in your design (ex. RAM, ROM, or Dual-port RAM), you can use the memory editor to create a memory initialization file to initialize your memory block For Simulation –You can create an initialization file to initialize your memory during simulation

40. © 2000 Altera Corporation 40 Menu Bar: File > New > Other Files tab Hex Document Mif Document Memory Editor - Create New File Create memory file

41. © 2000 Altera Corporation 41 Memory Editor - Create New File Create memory file –Enter Number of Words and Word Size

42. © 2000 Altera Corporation 42 Words OR Cells Memory Editor - Create New File Opens memory editor window with the required number of words and word size

43. © 2000 Altera Corporation 43 Memory Editor - Options Changing some options of memory editor –View  Select from available options Show ASCII Equivalents Cell Per Row

44. © 2000 Altera Corporation 44 Memory Editor - Options Changing radix settings of memory editor –View  Address/Memory Radix Memory Radix Address Radix

45. © 2000 Altera Corporation 45 Memory Editor - Edit Contents Create memory file –Edit contents of the memory file Select the word and type in a value OR Select the word and right click to select an option from the pop-up menu

46. © 2000 Altera Corporation 46 Memory Editor - Save File Create memory file –Save the memory file as.hex or.mif file.

47. © 2000 Altera Corporation 47 Need to Edit Memory Size Contents? Quartus Provides the Memory Size Wizard –Edit Word Size –Edit Number of Words –Specify How to Handle Word Size Change Increasing Word Size –Pad Words –Combine Words Decreasing Word Size –Truncate Words From Left –Truncate Words From Right. Memory Editor - Memory Size Wizard

48. © 2000 Altera Corporation 48 1. Open Memory File Memory Editor - Memory Size Wizard 2. Select the Memory Size Wizard

49. © 2000 Altera Corporation 49 Memory Editor - Memory Size Wizard Decreasing Memory Size 3a. How should Quartus handle excess bits? - Truncate MSBs - Truncate LSBs - Split Words/Increase Memory Depth 16 bits 8 bits To

50. © 2000 Altera Corporation 50 Memory Editor - Memory Size Wizard Increasing Memory Size 16 bits 32 bits 3b. How should Quartus pad words? - Combine Words - Sign Extend (Signed) - Pad MSBs With Zeros (Unsigned) To

51. © 2000 Altera Corporation 51 Memory Editor - Memory Size Wizard 4. Select New Memory Depth 4. Click on Finish

52. © 2000 Altera Corporation 52 EDA Interfaces Introduction Quartus can interface with industry-standard EDA tools that generate an EDIF 200 netlist file, a VHDL 1987 netlist file, VHDL 1993 netlist file, or a Verilog HDL netlist file NativeLink interface provides truly seamless integration with third-party EDA software tools –Quartus and EDA tools pass information/commands in background –Designers can complete entire designs without “leaving” their tools

53. © 2000 Altera Corporation 53 Introduction to Quartus Design Flows Quartus allows for three possible design flows : –Quartus Driven Flow: User launches other EDA tools from Quartus No need to learn 3rd party EDA tool –Vendor Driven Flow: User runs Quartus in the background from the 3rd party EDA tools –File Based Flow: Very little integration between Quartus and 3rd party EDA tools

54. © 2000 Altera Corporation 54 Quartus Driven Flow –EDA tools launched from within Quartus –Code level integration Cross probing and error location –Quartus automatically generates the netlists or reads in the netlists based on the tool –User doesn’t have to learn the setup and the flow Synthesis Tool Tcl COM (C++, VBScript) API Cross Probe Error Locate Quartus drives the third party EDA software

55. © 2000 Altera Corporation 55 Vendor Driven Flow –Offers the tightest code-level integration between tools –Quartus appears ‘Native’ in third party EDA software Third party EDA software drives Quartus Synthesis Tool Tcl COM (C++, VBScript) Cross Probe Error Locate API

56. © 2000 Altera Corporation 56 NativeLink Features Minimizes designer interaction with different EDA tools –Allows designers to complete their designs using as little as one tool Cross-referencing –Nodes from place-and-route result can be traced back to HDL code across from Quartus to a synthesis tool Improved Quality of Results (QoR) –Nativelink lets synthesis tools map directly into the fundamental building block of an architecture Iterative Compile –Improves QoR from synthesis tools –Allows Quartus to pass routing delay information after place-and- route back to the synthesis tools –Synthesis tools can then re-synthesize the design based on the feedback

57. © 2000 Altera Corporation 57 Quartus NativeLink interface is comprised of two components: –External Files: WYSIWYG (What You See Is What You Get) ATOM netlist files (EDIF, Verilog, VHDL) cross reference files (ex. xrf), timing files (ex. sdo) etc. –Application Programming Interface (API) Functions - a pre- defined interface EDA Partners API External Files NativeLink Quartus

58. © 2000 Altera Corporation 58 WYSIWYG ATOM Primitives A set of design primitives that support WYSIWYG compilation Provides direct control of how a design is technology mapped to a specific target device Helps synthesis vendors provide an optimal realization of a design for a device architecture WYSIWYG elements in the design are translated as directly as possible for fitting and routing purposes

59. © 2000 Altera Corporation 59 WYSIWYG Compilation FlowEDASynthesisPartnerEDASynthesisPartner EDIF Verilog VHDL Design Input Files with WYSIWYG Primitives Netlist Extraction Database Builder Synthesis Place & Route QUARTUS

60. © 2000 Altera Corporation 60 SYNTHESIS TOOL ATOM Netlist SDF File Device Database & Delay Annotator EDIF VHDL Verilog Area & Timing Constraints Partial Placement Final Placement Routing COMPILERCOMPILER Good Timing Estimation Better Timing Estimation Best Timing Estimation QUARTUS Iterative Compilation Flow

61. © 2000 Altera Corporation 61 Synthesis Tools Design Compiler FPGA Express 1 FPGA Compiler FPGA Compiler II Altera Edition General Version Leonardo Spectrum Synplify Simulation Tools ModelSim Verilog-XL Timing Analyzers: Motive Primetime Tools Supported by NativeLink 1 1 1 Note 1: These synthesis tools generate WYSIWYG ATOM netlists and support iterative compile capability

62. © 2000 Altera Corporation 62 Non-NativeLink Supported EDA Tools Synthesis Tools –Design Architect –ViewDraw Simulation Tools –VCS/VCSI –VSS –Speed Wave

63. © 2000 Altera Corporation 63 Quartus Driven Flow Project > EDA Tool Settings... ATOM netlist is automatically generated when you choose a NativeLink EDA Tool The correct data format is automatically chosen Quartus Driven Flow

64. © 2000 Altera Corporation 64 EDA Driven Flow Run Quartus in the background: Background Compile

65. © 2000 Altera Corporation 65 File Based Flow: Non-NativeLink If a non-NativeLink EDA Tool generates a VHDL, Verilog, EDIF file, then specify a.lmf for that file format Can be EDIF, VHDL, or Verilog Select a library mapping file (lmf) Project > EDA Tool Settings... Select Custom Select Settings...

66. © 2000 Altera Corporation 66 Quartus Projects

67. © 2000 Altera Corporation 67 Project Definitions Quartus Project: –A collection of related design files and libraries –Must have at least one designated top level entity –Targets a single device or can be partitioned into multiple devices –Stores project settings in Project Settings File (.PSF)

68. © 2000 Altera Corporation 68 Agenda New Project Wizard –Quick way to create a new project –Easy way to import an existing MAX+PLUS II project Project Menu –Edit existing project settings –Non-Wizard settings Project Settings File (.PSF) Project Navigator

69. © 2000 Altera Corporation 69 Creating a New Project 1. Invoke New Project Wizard 3. Name of Project. Recommendation: Use top- level design entity 2. Select Working directory

70. © 2000 Altera Corporation 70 4. Add design files - Graphic (.BDF,.GDF) - AHDL - VHDL - Verilog - EDIF Notes: All files in the project directory do not need to be added Add top level file if file name and entity name are not the same 5. Add user library pathnames and files Creating a New Project

71. © 2000 Altera Corporation 71 5(cont.) Add user library pathnames and files User Libraries (ex. MegaWizard functions) MegaCores/AMPP libraries Pre-compiled VHDL packages Browse to file and click on Add. Creating a New Project

72. © 2000 Altera Corporation 72 6. Review results and click on Finish Creating a New Project

73. © 2000 Altera Corporation 73 New Project (Completed) Project Name & Directory

74. © 2000 Altera Corporation 74 MAX+PLUS II to Quartus Converting MAX+PLUS II designs to Quartus: –Browse to project directory –Set top level file/entity –No need to add other files in directory –Add: Any files not located in same directory Any user directories as libraries Notes - Any Graphic Design File (.GDF) from MAX+PLUS II that is edited within Quartus can only be saved as a Block Diagram File (.BDF) by Quartus - Symbols with.GDF files may have to be updated - The Assignment & Configuration File (.ACF) from MAX+PLUS II is not recognized by Quartus

75. © 2000 Altera Corporation 75 Project Menu Edit the settings for an existing project –Adding/removing files or libraries Non-Wizard project settings –HDL interface –Third Party EDA Flow –Timing Settings (not discussed) –Revision Control (not discussed) Note: All Project settings except project name and top level entity default to the settings of the previously opened project

76. © 2000 Altera Corporation 76 Editing Project Settings Open the Existing Project Existing project must first be opened to edit the settings

77. © 2000 Altera Corporation 77 Editing Project Settings To add/remove project files Adding - Browse to file - Click Add Removing - Select file from list - Click Remove Access via the General Settings dialog box

78. © 2000 Altera Corporation 78 Editing Project Settings To add/remove project libraries Adding - Browse to directory - Click Add Removing - Select library from list - Click Remove

79. © 2000 Altera Corporation 79 VHDL Input Files Select VHDL version Enter Library names when directly compiling VHDL files with Quartus that contain user-created packages If gate level VHDL netlist file is used, specify mapping file (discussed later)

80. © 2000 Altera Corporation 80 Verilog Input Files If gate level Verilog netlist file is used, specify mapping file (discussed later)

81. © 2000 Altera Corporation 81 Project Settings File (PSF) Stores all project setting information Automatically generated by Quartus Quartus default file name is Can be manually edited inside Quartus

82. © 2000 Altera Corporation 82 Sample Project Settings File (PSF) DEFAULT_LOGIC_OPTIONS { DUPLICATE_LOGIC_EXTRACTION = ON; AUTO_TURBO_BIT = ON; AUTO_OPEN_DRAIN_PINS = ON; AUTO_PARALLEL_EXPANDERS = ON; AUTO_OUTPUT_REGISTERS = OFF; AUTO_INPUT_REGISTERS = OFF; AUTO_DELAY_CHAINS = ON; AUTO_CASCADE_CHAINS = ON; AUTO_CARRY_CHAINS = ON; PARALLEL_EXPANDER_CHAIN_LENGTH = 16; CASCADE_CHAIN_LENGTH = 2; CARRY_CHAIN_LENGTH = 32; NOT_GATE_PUSH_BACK = ON; SLOW_SLEW_RATE = OFF; STATE_MACHINE_PROCESSING = AUTO; } DEFAULT_TIMING_REQUIREMENTS { IGNORE_REQUIREMENTS_FOR_FITTER = ON; CUT_OFF_IO_PIN_FEEDBACK = ON; CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; CUT_OFF_READ_DURING_WRITE_PATH = ON; } PROJECT_INFO(test) { } THIRD_PARTY_EDA_TOOLS(test) { } Default Logic Options (partial listing) Timing Analysis Information EDA Tool Information

83. © 2000 Altera Corporation 83 Project Navigator Graphical display used to study project relationships Active in both Compilation and Simulation modes Three views –Hierarchies view –Files view –Design Units view

84. © 2000 Altera Corporation 84 Hierarchy View –Displays Project Hierarchy after project is analyzed –Can be used to make assignments Views of the Project Navigator

85. © 2000 Altera Corporation 85 Views of the Project Navigator Files View –Shows all files in the project –All source files appear under Design Files –Simulation files, include files, etc., appear under Other Files

86. © 2000 Altera Corporation 86 Views of the Project Navigator Design Unit view –Displays each design unit a design entity that can be used together with gates, registers, and megafunctions in a design file –Displays type, e.g. AHDL entity –Details the File in which it is instantiated Design Unit Associated Design File

87. © 2000 Altera Corporation 87 Project Summary Use Project Wizard to create new projects Use Project Menu dialog boxes to –Edit existing project settings –Set up Third Party interface Use Project Navigator to study file and entity relationships within the project