1. CHAPTER 5 Configuration, Reconfiguration and Security

2. Agenda Configuration basics –Controller structure –Frame structure –Different modes Reconfiguration –Modular –Differential –Partial 3DES and AES decryption

3. Config. Memory Related to Logic

4. Frame Shifter Related to Config.cells

5. Config. Sequence of Actions 1. Device Power Up 2. Clear the Configuration Memory 3. Sample the Mode Pins (described shortly) 4. Synchronize 5. Check Device ID 6. Load the configuration data 7.Check the CRC 8.Startup

6. Virtex Configuration Modes Note: Spartan 3E adds new modes with SPI and Byte Parallel Interface

7. Bitstream In, Config. Data Out

8. General Serial Configuration Model

9. Master Serial Mode Note

10. Master/Slave Serial Mode Note:

11. M/S Serial config. From Parallel EPROM

12. General Parallel Config. Model

13. Single Master SelectMap Mode

14. Single Master Config. From Micro/CPLD

15. Multi SelectMap Config.

16. JTAG Configuration

17. Configuration Controller

18. Reconfiguration Field upgrade – changing the design when it is installed at a remote site. Feature enhancement – adding features to an already deployed design. Reconfigurable coprocessor- changing a coprocessor function Modify connections on a printed circuit board – reroute existing connections Self reconfiguration (or dynamic reconfiguration) where an FPGA modifies itself Self correcting circuits – circuits that recover from failure, automatically

19. Configuration Column Sequencing First frame SetSecond Frame SetThird Frame Set

20. External Config. Controller

21. Scrub Controller Used with Triple Modular Redundancy to virtually eliminate single event upset errors due to nuclear radiation

22. Modular Partial Reconfiguration

23. Bus Macro

24. 3DES Encryption/Decryption Flow Path taken by iMPACT Path taken by FPGA

25. Configuration Decryptor

26. Decryption/Configuration Interaction

27. Configuration Close Configuration offers more options than you might expect –Many modes –Reconfiguration/partial reconfiguration –Decryption Lots of future work can be done here, to offer new operation models So far, nobody has built a serious “cache controller” that makes a coprocessor automatically sense the need to become a new function...