1. The Tiny Encryption Algorithm (TEA) Chip Ely V. Soto and Todd T. Wilkins 6 December 2001

2. What The Chip Does This chip is a scalable CMOS implementation of the tiny encryption algorithm developed in software by David Wheeler and Roger Needham of Cambridge University, England. The chip receives a serial input data stream from the user, performs the operations of the algorithm, and delivers a serial data stream of ciphertext to the user.

3. The Algorithm Below is the Tiny Encryption Algorithm: void code(long* v, long* k) { unsigned long y=v[0], z=v[1], sum=0, /* set up */ delta=0x9e3779b9, n=32; /* a key schedule constant */ while (n-- > 0) { /* basic cycle start */ sum += delta; y += (z >5)+k[1]; z += (y >5)+k[3]; } /* end cycle */ v[0]=y; v[1]=z; }

4. Changes to the Algorithm Due to the complexities inherent in the design, some modifications to the algorithm are implemented in hardware: No looping structure. User can accomplish this manually. Data word size reduced from 32 bits to 8 bits. Algorithm still functions, but strength suffers.

5. SR-16 The Block Diagram SR-16 4-bit Counter SERIAL IN 4 3 4-input NOR 8-bit Adder 8-bit Adder DELTA 8-bit Adder k[0] k[1] 0000 00000 8-bit Adder 8 8 8-bit XOR 4 3 8-bit Adder 8-bit Adder k[2] k[3] 0000 00000 8-bit Adder 8 8-bit XOR 8-bit Adder 8 8-bit Adder zy SR-16/Mux SERIAL OUT CLK EXT CLK CLK/16

6. Power On Reset Circuit Because some of the circuit components need to be started in a known state, a power on reset circuit has been developed. RC circuit that starts low and gradually reaches V DD. During low period, registers are reset. Once high, circuit is functional.

7. Counter Circuit A difficult part of the design was building the counter. Design requires feedback. Master-slave JK flip-flop design with integrated multiplexers. 1-bit counter Multiplexer

8. DeltaSum Circuit The DeltaSum Circuit controls the adder for looping. This counter is controlled externally by the user for enhanced user control over security. AND gates are used with RESETDELTA input to clear the counter. 8-bit Adder Shift Register AND Gates

9. The Entire Circuit Total Transistor Count Without pads: 3,342 With pads: 4,906 Critical Delay: 21.85 ns Clock: 45.76 MHz

10. Pin Outs 363534G33313029 27 26 25 24 23 22 21 20 17161513V121110 8 7 6 5 4 3 2 1 919 28 18 SERIALIN CLKSERIN RESETSERCNT OVERFLOW RESETDELTA CLKDELTA DELTALSB DELTAMSB SERIALOUT CNTOVRD