1. 178220 Digital Logic Design @Department of Computer Engineering KKU.1 Chapter 5 Sequential Systems Latches and Flip-flops Synchronous Counter Asynchronous Counter

2. 178220 Digital Logic Design @Department of Computer Engineering KKU. 2 Introduction Up to now everything has been combinational – the output at any instant of time depends only on what inputs are at the time. Later on of this course: sequential systems – systems that have memory. Thus, the output will depend not only on the present input but also on the past history – what has happened earlier.

3. 178220 Digital Logic Design @Department of Computer Engineering KKU. 3 Clock Signals Two versions of a clock signal are as below. In the first, the clock signal is 0 half of the time and 1 half of the time. In the second, it is 1 for a shorter part of the cycle. The period of the signal (T on the diagram) is the length of one cycle. The frequency is the inverse (1/T). T

4. 178220 Digital Logic Design @Department of Computer Engineering KKU. 4 Conceptual View of a Sequential System

5. 178220 Digital Logic Design @Department of Computer Engineering KKU. 5 Terminology State: what is stored in memory. State table: shows for each input combination and each state, what the output is and what the next state is – what is to be stored in memory after the next clock. State diagram (or state graph): a graphical representation of the state table.  (Finite) State Machine

6. 178220 Digital Logic Design @Department of Computer Engineering KKU. 6 State Table and State Diagram qq*z x=0x=1x=0x=1 AAB00 BCB10 CAD00 DCC00 A D B C 0/0 0/11/0 0/0 1/0 X/0 State tableState diagram present state next state output input

7. 178220 Digital Logic Design @Department of Computer Engineering KKU. 7 The next state is a function of the present state and the input. The output also depends on the present state (and on the input). It may change on a clock transition, but it may change where the input changes, as well. In state diagram, there must be one path from each state for each possible input combination.

8. 178220 Digital Logic Design @Department of Computer Engineering KKU. 8 Moore vs. Mealy Models Moore model circuit (state-based)  the outputs depend on the present state of the system but not on the inputs. Mealy model circuit (input-based)  the outputs depend on the inputs as well as the present state of the system.

9. 178220 Digital Logic Design @Department of Computer Engineering KKU. 9 Moore: A system with no input and three outputs, that represent a number from 0 to 7, such that the outputs cycle through the sequence 0 3 2 4 1 5 7 and repeat on consecutive clock inputs. Mealy: A system with two inputs,X 1 and X 2, and three outputs, Z 1, Z 2 and Z 3, that represent a number from 0 to 7, such that the output counts up if X 1 =0 and down if X 1 =1 and recycles if X 2 =0 and saturates if X 2 =1. Thus, the following output sequences might be seen:

10. 178220 Digital Logic Design @Department of Computer Engineering KKU. 10 X 1 =0 X 2 =00 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7.. X 1 =0 X 2 =1 0 1 2 3 4 5 6 7 7 7 7 7 7.. X 1 =1 X 2 =0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0.. X 1 =1 X 2 =1 7 6 5 4 3 2 1 0 0 0 0 0 0..

11. 178220 Digital Logic Design @Department of Computer Engineering KKU. 11 Design Process of Sequential Systems Table 5.1 Page 338  State table  Timing trace  State table with binary states  Truth table  K-map  equations

12. 178220 Digital Logic Design @Department of Computer Engineering KKU. 12 Design Process of Sequential Systems qq*z x=0x=1x=0x=1 AAB00 BCB10 CAD00 DCC00 clk123456789101112 x0110101011 qAABBCDCDCDC z000100000000 State table Timing trace

13. 178220 Digital Logic Design @Department of Computer Engineering KKU. 13 Design Process of Sequential Systems q1q1 q 1 *q 2 *z x=0x=1x=0x=1 00 0100 100110 10001100 10 00 State assignment State table with binary states qq1q1 q2q2 A00 B01 C10 D 11

14. 178220 Digital Logic Design @Department of Computer Engineering KKU. 14 Design Process of Sequential Systems xq1q1 q2q2 q1*q1*q2*q2*z 000000 001101 010000 011100 100010 101010 110110 111100 State assignment Truth table for system design 11 x q2q2 11 q2’q2’q2’q2’ x’ q1q1 q1’q1’ q1q2x q1q2x

15. 178220 Digital Logic Design @Department of Computer Engineering KKU. 15 Latches and Flip-flops A latch is a binary storage device, composed of two or more gates, with feedback. The latch can store either a 0 (Q = 0 and P = 1) or a 1 (Q = 1 and P = 0) The P output is just labelled

16. 178220 Digital Logic Design @Department of Computer Engineering KKU. 16 Latches (cont.) Edge-triggered rising/leading edge-triggered falling/trailing edge-triggered Level-triggered high level-triggered low level-triggered

17. 178220 Digital Logic Design @Department of Computer Engineering KKU. 17 Latches (cont.) Example: a latch constructed with 2 NORs. S P R Q The equations for this system: and Normal storage stage  both inputs inactive (S = R = 0). and

18. 178220 Digital Logic Design @Department of Computer Engineering KKU. 18 Latches (cont.) S P R Q Case 1: If S=1 and R=0 Case 2: If S=0 and R=1 Case 3: Finally, the flip-flop is not operated with both S and R active (=1).

19. 178220 Digital Logic Design @Department of Computer Engineering KKU. 19 Latches (cont.)  D flip-flops (Delay flip-flops)  SR flip-flops (Set/Reset flip-flops)  T flip-flops (Toggle flip-flops)  JK flip-flops

20. 178220 Digital Logic Design @Department of Computer Engineering KKU. 20 D flip-flops Dqq* 000 010 101 111 0 1 1 1 0 0 D D 00 11  q*=D

21. 178220 Digital Logic Design @Department of Computer Engineering KKU. 21 D flip-flops (cont.)

22. 178220 Digital Logic Design @Department of Computer Engineering KKU. 22 D flip-flops (cont.) Two D flip-flops

23. 178220 Digital Logic Design @Department of Computer Engineering KKU. 23 D flip-flops (cont.) With Clear and Preset Dqq* 01XX1 Static 10XX0 Immediate 00XX- Not allowed 11000 Clocked (as before) 11010 11101 11111

24. 178220 Digital Logic Design @Department of Computer Engineering KKU. 24 D flip-flops + Clear and Preset (cont.)

25. 178220 Digital Logic Design @Department of Computer Engineering KKU. 25 SR flip-flops SRqq* 0000 0011 0100 0110 1001 1011 110- 111- SR 00q 010 101 11- 0 1 10 00 10 01 00 01 SR  1 x1 q R x R’ 1 q’ SS’ SR q Not allowed

26. 178220 Digital Logic Design @Department of Computer Engineering KKU. 26 SR flip-flops (cont.)

27. 178220 Digital Logic Design @Department of Computer Engineering KKU. 27 T flip-flops Tqq* 000 011 101 110 T 0q 1 0 1 1 0 1 0 T  q*=T  q

28. 178220 Digital Logic Design @Department of Computer Engineering KKU. 28 JK flip-flops JKqq* 0000 0011 0100 0110 1001 1011 1101 1110 JK 00q 010 101 11 0 1 10 11 00 10 01 11 00 01 JK  1 1 q K 1 K’ 1 q’ JJ’ JK q

29. 178220 Digital Logic Design @Department of Computer Engineering KKU. 29 JK flip-flops (cont.)

30. 178220 Digital Logic Design @Department of Computer Engineering KKU. 30 Analysis of Sequential Systems Figure 5.21 Page 342  Circuit  Equations  State table  Timing trace  Timing diagram  Equations A*,B*  State diagram

31. 178220 Digital Logic Design @Department of Computer Engineering KKU. 31 Flip-flop Design Techniques xq1q1 q2q2 q1*q1*q2*q2*z 000000 001100 010000 011101 100010 101010 110110 111101 From the truth table, it’s clear that We need to create the appropriate flip-flop design table to obtain a truth table for the flip-flop inputs. z=q 1 q 2 qq*Input(s) 00 01 10 11 Main truth table D flip-flops JK flip-flops SR flip-flops T flip-flops next

32. 178220 Digital Logic Design @Department of Computer Engineering KKU. 32 Design with D Flip-flop Dq* 00 11 q D 000 011 100 111 xq1q1 q2q2 D 1 =q 1 *D 2 =q 2 * 00000 00110 01000 01110 10001 10101 11011 11110  From the main truth table main truth table

33. 178220 Digital Logic Design @Department of Computer Engineering KKU. 33 Design with D Flip-flop (cont.) x q1q201 00 01 1 11 1 10 1 x q1q201 00 1 01 11 1 10 1

34. 178220 Digital Logic Design @Department of Computer Engineering KKU. 34 Implementation using D Flip-flops back

35. 178220 Digital Logic Design @Department of Computer Engineering KKU. 35 Design with JK Flip-flop JKq* 00q 010 101 11 q JK 000X 011X 10X1 11X0 xq1q1 q2q2 q1*q1*q2*q2*J1J1 K1K1 J2J2 K2K2 000000X0X 001100XX1 01000X10X 01110X1X1 100010X1X 101011XX1 11011X01X 11110X0X0   From the main truth table main truth table

36. 178220 Digital Logic Design @Department of Computer Engineering KKU. 36 Design with JK Flip-flop (cont.) x q1q201 00 01 1 11 XX 10 XX x q1q201 00 XX 01 XX 11 1 10 1 x q1q201 00 1 01 XX 11 XX 10 1 x q1q201 00 XX 01 11 11 1 10 XX J 1 K 1 J 2 K 2 back

37. 178220 Digital Logic Design @Department of Computer Engineering KKU. 37 Design with SR Flip-flop SRq* 00q 010 101 11- q SR 000X 0110 1001 11X0 xq1q1 q2q2 q1*q1*q2*q2*S1S1 R1R1 S2S2 R2R2 000000X0X 001100X01 01000010X 011100101 100010X10 101011001 11011X010 11110X0X0   From the main truth table main truth table

38. 178220 Digital Logic Design @Department of Computer Engineering KKU. 38 Design with SR Flip-flop (cont.) x q1q201 00 01 1 11 X 10 X x q1q201 00 XX 01 X 11 1 10 1 x q1q201 00 1 01 11 X 10 1 x q1q201 00 X 01 11 11 1 10 X J 1 K 1 J 2 K 2 back

39. 178220 Digital Logic Design @Department of Computer Engineering KKU. 39 Design with T Flip-flop Tq* 0q 1 q T 000 011 101 110 xq1q1 q2q2 q1*q1*q2*q2*T1T1 T2T2 0000000 0011001 0100010 0111011 1000101 1010111 1101101 1111000  From the main truth table main truth table

40. 178220 Digital Logic Design @Department of Computer Engineering KKU. 40 Design with T Flip-flop (cont.) x q1q201 00 01 1 11 1 10 1 x q1q201 00 1 01 11 11 1 10 1 back

41. 178220 Digital Logic Design @Department of Computer Engineering KKU. 41 Quick method for JK Because Notice that when q=0 And when q=1

42. 178220 Digital Logic Design @Department of Computer Engineering KKU. 42 Quick method for JK (cont.) state table to maps

43. 178220 Digital Logic Design @Department of Computer Engineering KKU. 43 Quick method for JK (cont.)  First column of J 1 and K 1 Second column  of J 1 and K 1 Conventional qq*JK 000X 011X 10X1 11X0

44. 178220 Digital Logic Design @Department of Computer Engineering KKU. 44 Quick method for JK (cont.) Computation of J 2 and K 2 Conventional

45. 178220 Digital Logic Design @Department of Computer Engineering KKU. 45 Quick method for JK (cont.) Computation of J 1 and K 1 Quick method

46. 178220 Digital Logic Design @Department of Computer Engineering KKU. 46 Design of Synchronous Counters Design a decimal or decade counter using JK flip-flops: DCBAD*C*B*A* 00000001 00010010 00100011 00110100 01000101 01010110 01100111 01111000 10001001 10010000 1010xxxx …………………… 1111Xxxx 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, …

47. 178220 Digital Logic Design @Department of Computer Engineering KKU. 47 Design of Synchronous Counters (cont.) DC BA X1 X 1XX XX DC BA 1X 1X 1XX 1XX DC BA X 11X XX 11XX DC BA 11X1 X XX 11XX D* C* B* A*

48. 178220 Digital Logic Design @Department of Computer Engineering KKU. 48 DC BA X1 X 1XX XX DC BA XX XX 1XX XX DC BA XXX XXX1 XXXX XXXX D* JDJDJDJD KDKDKDKD From the main truth table of the D*main truth table of the D* Design of Synchronous Counters (cont.)

49. 178220 Digital Logic Design @Department of Computer Engineering KKU. 49 Design of Synchronous Counters (cont.) DC BA 1X 1X 1XX 1XX DC BA XX XX 1XXX XXX DC BA XXX XXX X1XX XXX C* JCJCJCJC KCKCKCKC From the main truth table of the C*main truth table of the C*

50. 178220 Digital Logic Design @Department of Computer Engineering KKU. 50 Design of Synchronous Counters (cont.) DC BA X 11X XX 11XX DC BA X 11X XXXX XXXX DC BA XXXX XXXX 11XX XX B* JBJBJBJB KBKBKBKB From the main truth table of the C*main truth table of the C*

51. 178220 Digital Logic Design @Department of Computer Engineering KKU. 51 Design of Synchronous Counters (cont.) DC BA 11X1 X XX 11XX DC BA 11X1 XXXX XXXX 11XX DC BA XXXX 11X1 11XX XXXX A* JAJAJAJA KAKAKAKA From the main truth table of the A*main truth table of the A*

52. 178220 Digital Logic Design @Department of Computer Engineering KKU. 52 Example: A Base-16 Counter DCBAD*C*B*A*remark 00000001 0101 00010010 1212 00100011 2323 00110100 3434 01000101 4545 01010110 5656 01100111 6767 01111000 7878 10001001 8989 10011010 9A9A 10101011 ABAB 10111100 BCBC 11001101 CDCD 11011110 DEDE 11101111 EFEF 11110000 F0F0

53. 178220 Digital Logic Design @Department of Computer Engineering KKU. 53 Example: A Base-16 Counter (cont.) J D = K D = CBA DC BA 11 11 11 11 DC BA 11 11 11 11 J C = K C = BA

54. 178220 Digital Logic Design @Department of Computer Engineering KKU. 54 Example: A Base-16 Counter (cont.) J B = K B = A DC BA 1111 1111 DC BA 1111 1111 J A = K A = 1

55. 178220 Digital Logic Design @Department of Computer Engineering KKU. 55 Example: An Up/Down Counter XCBAC*B*A*remark 0000001 0101 0001010 1212 0010011 2323 0011100 3434 0100101 4545 0101110 5656 0110111 6767 0111000 7070 1000111 0707 1001000 1010 1010001 2121 1011010 3232 1100011 4343 1101100 5454 1110101 6565 1111110 7676 J A = K A = 1 J B = K B = xA + xA J C = K C = xBA + xBA

56. 178220 Digital Logic Design @Department of Computer Engineering KKU. 56 Example: 0, 3, 2, 4, 1, 5, 7, and repeat q1q1 q2q2 q3q3 q1*q1*q2*q2*q3*q3*remark 000011 0303 001101 1515 010100 2424 011010 3232 100001 4141 101111 5757 110XXX 6X6X 111000 7070

57. 178220 Digital Logic Design @Department of Computer Engineering KKU. 57 Example: 0, 3, 2, 4, 1, 5, 7, and repeat (cont.)

58. 178220 Digital Logic Design @Department of Computer Engineering KKU. 58 Example: 0, 3, 2, 4, 1, 5, 7, and repeat (cont.)

59. 178220 Digital Logic Design @Department of Computer Engineering KKU. 59 Design of Asynchronous Counters Page 350…. Figure 5.31(2-bit counter)&5.32(timing delay) Advantage:  Simplicity of the hardware  no combinational logic required Disadvantage:  Speed

60. 178220 Digital Logic Design @Department of Computer Engineering KKU. 60 Derivation of State tables and State Diagrams Consider the problem: Another way of wording this same problem is A Mealy system with one input x and one output z such that z = 1 iff x has been 1 for three consecutive clock times. A system with one input x and one output z such that z = 1 at a clock time iff x is currently 1 and was also 1 at the previous two clock times.

61. 178220 Digital Logic Design @Department of Computer Engineering KKU. 61 A sample input/output trace is x01111111011011101 z000111110000001000 q 1 *q 2 *z q1q1 q2q2 x=0x=1x=0x=1 00000100 01101100 10000100 11101101 First approach: save the previous 2 inputs. Knowing them and the present input  output. Just discard the older input stored in memory and store the newer one plus the current input.

62. 178220 Digital Logic Design @Department of Computer Engineering KKU. 62 Second approach: store in memory the number of consecutive 1’s as follows:  A  Anone, that is, the last input was 0  B  Bone  C  Ctwo or more q*z qx=0x=1x=0x=1 ABCABC AAAAAA BCCBCC 00 00 01 A B C 0/0 1/0 no 1’s one 1 two or more 1’s 0/0 1/1 0/0 1/0

63. 178220 Digital Logic Design @Department of Computer Engineering KKU. 63 The second approach requires only 3 states, whereas the first requires 4. Both, however, use 2 flip-flops. Consider: the system produces a 1 if the input has been 1 for 25 consecutive clock times. Now the first approach requires to store the last 24 inputs and a state table of 2 24 rows. The second approach requires 25 states which can be coded with 5 flip-flops.