1. Sequential Logic Review
Material in this review is from Contemporary Logic Design
by Randy Katz

2. Sequential Circuits Circuits with Feedback State is memory
Outputs = f(inputs, past inputs, past outputs)
Basis for building "memory" into logic circuits
Door combination lock is an example of a sequential circuit
State is memory
State is an "output" and an "input" to combinational logic
Combination storage elements are also memory
value(4 bits)
new
equal
reset
Ld1
Ld2
Ld3
mux control C1 C2 C3
multiplexer
comb. logic
comparator
state
clock
equal
open/closed
Reg: C1, C2, C3
need a clock to load
value

3. Digital combination lock state diagram
States: 5 states
represent point in execution of machine
each state has outputs
Transitions: 6 from state to state, 5 self transitions, 1 global
changes of state occur when clock says its ok
based on value of inputs
Inputs: reset, new, results of comparisons
Output: open/closed
ERR
closed
C1!=value & new
C2!=value & new
C3!=value & new S1 S2 S3
OPEN
reset
closed
closed
closed
open
C1==value & new
C2==value & new
C3==value & new
not new
i.e., no digits entered
not new
not new

4. Edge-Triggered Flip-Flops
Sensitive to inputs only near edge of clock signal (not while high) Q D
Clk=1 R S D’ Q’
holds D' when
clock goes low
negative edge-triggered D flip-flop (D-FF)
4-5 gate delays
must respect setup and hold time constraints to successfully capture input
holds D when clock goes low
characteristic equation Q(t+1) = D

5. Edge-Triggered Flip-Flops (cont’d)
Step-by-step analysis Q D
Clk=0 R S D’ Q
new D
Clk=0 R S D D’
new D  old D
when clock goes high-to-low
data is latched
when clock is low
data is held

6. Edge-Triggered Flip-Flops (cont’d)
Positive edge-triggered
Inputs sampled on rising edge; outputs change after rising edge
Negative edge-triggered flip-flops
Inputs sampled on falling edge; outputs change after falling edge
100 D
CLK
Qpos
Qpos'
Qneg
Qneg'
positive edge-triggered FF
negative edge-triggered FF

7. Timing Methodologies Rules for interconnecting components and clocks
Guarantee proper operation of system when strictly followed
Approach depends on building blocks used for memory elements
Focus on systems with edge-triggered flip-flops
Found in programmable logic devices
Many custom integrated circuits focus on level-sensitive latches
Basic rules for correct timing:
(1) Correct inputs, with respect to time, are provided to the flip-flops
(2) No flip-flop changes state more than once per clocking event

8. Timing Methodologies (cont’d)
Definition of terms
clock: periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level
setup time: minimum time before the clocking event by which the input must be stable (Tsu)
hold time: minimum time after the clocking event until which the input must remain stable (Th)
input
clock
Tsu Th
data D Q D Q
clock
there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized
stable
changing
data
clock

9. Comparison of Latches and Flip-Flops
D Q D
CLK
Qedge
Qlatch
CLK
positive edge-triggered flip-flop
D Q G
CLK
transparent (level-sensitive) latch
behavior is the same unless input changes
while the clock is high

10. Typical Timing Specifications
Positive edge-triggered D flip-flop
Setup and hold times
Minimum clock width
Propagation delays (low to high, high to low, max and typical)
Th 0.5ns
Tw 3.3ns
Tplh 3.6ns 1.1ns
Tphl 3.6ns 1.1ns
Tsu 1.8ns D
CLK Q
data from
374 posedge
triggered
flip flop
all measurements are made from the clocking event that is, the rising edge of the clock

11. Cascading Edge-triggered Flip-Flops
Shift register
New value goes into first stage
While previous value of first stage goes into second stage
Consider setup/hold/propagation delays (prop must be > hold)
CLK IN Q0 Q1 D Q
OUT
100 IN Q0 Q1
CLK

12. Cascading Edge-triggered Flip-Flops (cont’d)
Why this works
Propagation delays exceed hold times
Clock width constraint exceeds setup time
This guarantees following stage will latch current value before it changes to new value In Q0 Q1
CLK
Tsu
4ns
Tsu
4ns
timing constraints
guarantee proper
operation of
cascaded components Tp
3ns Tp
3ns
assumes infinitely fast distribution of the clock Th
2ns Th
2ns

13. Clock Skew
The problem
Correct behavior assumes next state of all storage elements determined by all storage elements at the same time
This is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic
Effect of skew on cascaded flip-flops:
100 In Q0 Q1
CLK0
CLK1
CLK1 is a delayed
version of CLK0
In our design we expect
CLK1 and CLK0 arrive
at the same time
original state: IN = 0, Q0 = 1, Q1 = 1
due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1

14. Summary of Latches and Flip-Flops
Development of D-FF
Level-sensitive used in custom integrated circuit
Edge-triggered used in programmable logic devices
Good choice for data storage register
Historically J-K FF was popular but now never used
Similar to R-S but with 1-1 being used to toggle output (complement state)
Good in old days of TTL/SSI (more complex input function: D = JQ' + K'Q
Not a good choice for PALs/PLAs as it requires 2 inputs
Can always be implemented using D-FF
Preset and clear inputs are highly desirable on flip-flops
Used at start-up or to reset system to a known state

15. Dealing with Synchronization Failure
Probability of failure can never be reduced to 0, but it can be reduced
(1) slow down the system clock: this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems
(2) use fastest possible logic technology in the synchronizer
(3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail)
asynchronous
input Q
synchronized
input D Q D
Clk
synchronous system

16. Handling Asynchronous Inputs
Never allow asynchronous inputs to fan-out to more than one flip-flop
Synchronize as soon as possible and then treat as synchronous signal
Clocked
Synchronizer
Synchronous
System
Async Q0
Async Q0 D Q D Q D Q
Input
Input
Clock
Clock D Q Q1 D Q Q1
Clock
Clock

17. Handling Asynchronous Inputs (cont’d)
What can go wrong?
Input changes too close to clock edge (violating setup time constraint) In Q0 Q1
CLK
In is asynchronous and fans out to D0 and D1 one FF catches the signal, one does not
inconsistent state may be reached!

18. Registers Collections of flip-flops with similar controls and logic
Stored values somehow related (e.g., form binary value)
Share clock, reset, and set lines
Similar logic at each stage
Examples
Shift registers
Counters R S D Q
OUT1
OUT2
OUT3
OUT4
CLK
IN1
IN2
IN3
IN4
"0"

19. Shift Register Holds samples of input
Store last 4 input values in sequence
4-bit shift register: D Q IN
OUT1
OUT2
OUT3
OUT4
CLK

20. Universal Shift Register
Holds 4 values
Serial or parallel inputs
Serial or parallel outputs
Permits shift left or right
Load new input
left_in
left_out
right_out
clear
right_in
output
input s0 s1
clock
clear sets the register contents and output to 0 s1 and s0 determine the shift function s0 s1 function hold state shift right shift left load new input

21. Design of Universal Shift Register
Consider one of the four flip-flops
New value at next clock cycle:
Nth cell
to N-1th cell
to N+1th cell Q D
CLK
clear s0 s1 new value 1 – – output output value of FF to left (shift right) output value of FF to right (shift left) input
CLEAR
s0 and s1 control mux 1 2 3
Q[N-1] (left)
Q[N+1] (right)
Input[N]

22. Pattern Recognizer Combinational function of input samples
In this case, recognizing the pattern 1001 on the single input signal D Q IN
OUT1
OUT2
OUT3
OUT4
CLK
OUT

23. Counters Sequences through a fixed set of patterns
In this case, 1000, 0100, 0010, 0001
If one of the patterns is its initial state (by loading or set/reset)
Mobius (or Johnson) counter
In this case, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 D Q IN
OUT1
OUT2
OUT3
OUT4
CLK D Q IN
OUT1
OUT2
OUT3
OUT4
CLK

24. Binary Counter Logic between registers (not just multiplexer)
XOR decides when bit should be toggled
Always for low-order bit, only when first bit is true for second bit, and so on D Q
OUT1
OUT2
OUT3
OUT4
CLK
"1"

25. Offset Counters Starting offset counters – use of synchronous load
"0" EN
D C B A
LOAD
CLK
CLR
RCO
QD QC QB QA
"1"
"0" "1" "1" "0"
Starting offset counters – use of synchronous load
e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, . . .
Ending offset counter – comparator for ending value
e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000
Combinations of the above (start and stop value) EN
D C B A
LOAD
CLK
CLR
RCO
QD QC QB QA
"1"
"0" "0" "0" "0"

26. State Machine Model
Values stored in registers represent the state of the circuit
Combinational logic computes:
Next state
Function of current state and inputs
Outputs
Function of current state and inputs (Mealy machine)
Function of current state only (Moore machine)
Inputs
Outputs
Next State
Current State
output logic
next state logic

27. State Machine Model (cont’d)
Inputs
Outputs
Next State
Current State
output logic
next state logic
States: S1, S2, ..., Sk
Inputs: I1, I2, ..., Im
Outputs: O1, O2, ..., On
Transition function: Fs(Si, Ij)
Output function: Fo(Si) or Fo(Si, Ij)
Clock
Next State
State 1 2 3 4 5

28. Comparison of Mealy and Moore Machines
Mealy Machines tend to have less states
Different outputs on arcs (n^2) rather than states (n)
Moore Machines are safer to use
Outputs change at clock edge (always one cycle later)
In Mealy machines, input change can cause output change as soon as logic is done – a big problem when two machines are interconnected – asynchronous feedback
Mealy Machines react faster to inputs
React in same cycle – don't need to wait for clock
In Moore machines, more logic may be necessary to decode state into outputs – more gate delays after
inputs
outputs
state feedback
reg
combinational logic for next state
logic for outputs
state feedback
inputs
outputs
reg
combinational logic for next state
logic for outputs

29. Example: Vending Machine
Release item after 15 cents are deposited
Single coin slot for dimes, nickels
No change
Reset N
Vending Machine FSM
Open
Coin Sensor
Release Mechanism D
Clock

30. Example: Vending Machine (cont’d)
Suitable Abstract Representation
Tabulate typical input sequences:
3 nickels
nickel, dime
dime, nickel
two dimes
Draw state diagram:
Inputs: N, D, reset
Output: open chute
Assumptions:
Assume N and D asserted for one cycle
Each state has a self loop for N = D = 0 (no coin) S0
Reset S1 N S2 D S3 N S4
[open] D S5
[open] N S6
[open] D S7
[open] N

31. Example: Vending Machine (cont’d)
Minimize number of states - reuse states whenever possible 0¢
Reset
symbolic state table
present inputs next output state D N state open 0¢ ¢ ¢ ¢ – – 5¢ ¢ ¢ ¢ – – 10¢ ¢ ¢ ¢ – – 15¢ – – 15¢ 1
10¢ D 5¢ N
15¢
[open] D N
N + D

32. Example: Vending Machine (cont’d)
Uniquely Encode States, binary encoding is selected
present state inputs next state output Q1 Q0 D N D1 D0 open – – – – – – – – – – –

33. Example: Vending Machine (cont’d)
Mapping to Logic
X X X X Q1 D1 Q0 N D D0
Open
D1 = Q1 + D + Q0 N
D0 = Q0’ N + Q0 N’ + Q1 N + Q1 D
OPEN = Q1 Q0

34. Example: Vending Machine (cont’d)
One-hot Encoding
present state inputs next state output Q3 Q2 Q1 Q0 D N D3 D2 D1 D0 open
D0 = Q0 D’ N’
D1 = Q0 N + Q1 D’ N’
D2 = Q0 D + Q1 N + Q2 D’ N’
D3 = Q1 D + Q2 D + Q2 N + Q3
OPEN = Q3

35. Equivalent Mealy and Moore State Diagrams
Moore machine
outputs associated with state
Mealy machine
outputs associated with transitions 0¢
[0]
10¢ 5¢
15¢
[1]
N’ D’ + Reset D N
N+D
N’ D’
Reset’
Reset 0¢
10¢ 5¢
15¢
(N’ D’ + Reset)/0
D/0
D/1
N/0
N+D/1
N’ D’/0
Reset’/1
Reset/0

36. Vending Machine (cont’d)
OPEN = Q1Q0 creates a combinational delay after Q1 and Q0 change
This can be corrected by retiming, i.e., move flip-flops and logic through each other to improve delay
OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D) = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
Implementation now looks like a synchronous Mealy machine
Common for programmable devices to have FF at end of logic

37. Finite State Machine Optimization
State Minimization
Fewer states require fewer state bits
Fewer bits require fewer logic equations
Encodings: State, Inputs, Outputs
State encoding with fewer bits has fewer equations to implement
However, each may be more complex
State encoding with more bits (e.g., one-hot) has simpler equations
Complexity directly related to complexity of state diagram
Input/output encoding may or may not be under designer control

38. Algorithmic Approach to State Minimization
Goal – identify and combine states that have equivalent behavior
Equivalent States:
Same output
For all input combinations, states transition to same or equivalent states
Algorithm Sketch
1. Place all states in one set
2. Initially partition set based on output behavior
3. Successively partition resulting subsets based on next state transitions
4. Repeat (3) until no further partitioning is required
states left in the same set are equivalent
Polynomial time procedure

39. State Minimization Example
Sequence Detector for 010 or 110
Input Next State Output
Sequence Present State X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0 S0 S3 S2 S1 S5 S6 S4
1/0
0/0
0/1

40. Method of Successive Partitions
Input Next State Output
Sequence Present State X=0 X=1 X=0 X=1
Reset S0 S1 S2 0 0
0 S1 S3 S4 0 0
1 S2 S5 S6 0 0
00 S3 S0 S0 0 0
01 S4 S0 S0 1 0
10 S5 S0 S0 0 0
11 S6 S0 S0 1 0
( S0 S1 S2 S3 S4 S5 S6 )
( S0 S1 S2 S3 S5 ) ( S4 S6 )
( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 )
( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 )
S1 is equivalent to S2
S3 is equivalent to S5
S4 is equivalent to S6

41. Minimized FSM State minimized sequence detector for 010 or 110
Input Next State Output
Sequence Present State X=0 X=1 X=0 X=1
Reset S0 S1' S1' 0 0
0 + 1 S1' S3' S4' 0 0
X0 S3' S0 S0 0 0
X1 S4' S0 S0 1 0 S0
S1’
S3’
S4’
X/0
1/0
0/1
0/0

42. More Complex State Minimization
Multiple input example
inputs here 10 01 11 00
S0 [1]
S2 [1]
S4 [1] S1
[0] S3 S5
present next state output state S0 S0 S1 S2 S S1 S0 S3 S1 S S2 S1 S3 S2 S S3 S1 S0 S4 S S4 S0 S1 S2 S S5 S1 S4 S0 S5 0
symbolic state transition table

43. Minimized FSM Implication Chart Method
Cross out incompatible states based on outputs
Then cross out more cells if indexed chart entries are already crossed out S1 S2 S3 S4 S5 S0
minimized state table
(S0==S4) (S3==S5)
present next state output state S0' S0' S1 S2 S3' S1 S0' S3' S1 S3' S2 S1 S3' S2 S0' S3' S1 S0' S0' S3' 0
S0-S1
S1-S3
S2-S2
S3-S4
S0-S1
S3-S0
S1-S4
S4-S5
S0-S0
S1-S1
S2-S2
S3-S5
S1-S0
S3-S1
S2-S2
S4-S5
S0-S1
S3-S4
S1-S0
S4-S5
S4-S0
S5-S5
S1-S1
S0-S4

44. State Assignment Strategies
Possible Strategies
Sequential – just number states as they appear in the state table
Random – pick random codes
One-hot – use as many state bits as there are states (bit=1 –> state)
Output – use outputs to help encode states
Heuristic – rules of thumb that seem to work in most cases
No guarantee of optimality – another intractable problem

45. One-hot State Assignment
Simple
Easy to encode, debug
Small Logic Functions
Each state function requires only predecessor state bits as input
Good for Programmable Devices
Lots of flip-flops readily available
Simple functions with small support (signals its dependent upon)
Impractical for Large Machines
Too many states require too many flip-flops
Decompose FSMs into smaller pieces that can be one-hot encoded
Many Slight Variations to One-hot
One-hot + all-0

46. Heuristics for State Assignment
Adjacent codes to states that share a common next state
Group 1's in next state map
Adjacent codes to states that share a common ancestor state
Adjacent codes to states that have a common output behavior
Group 1's in output map
i / j
i / k a b c
I Q Q+ O i a c j i b c k
c = i * a + i * b a b c
i / j
k / l
I Q Q+ O i a b j k a c l
b = i * a c = k * a
I Q Q+ O i a b j i c d j
j = i * a + i * c b = i * a d = i * c b d
i / j a c

47. Output-Based Encoding
Reuse outputs as state bits - use outputs to help distinguish states
Why create new functions for state bits when output can serve as well
Fits in nicely with synchronous Mealy implementations

48. Current State Assignment Approaches
For tight encodings using close to the minimum number of state bits
Heuristic approaches are not even close to optimality
Used in custom chip design
One-hot encoding
Easy for small state machines
Generates small equations with easy to estimate complexity
Common in FPGAs and other programmable logic
Output-based encoding
Ad hoc - no tools
Most common approach taken by human designers
Yields very small circuits for most FSMs