1. Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory1 June 2001 Front End Module Circuit 12 Channel Detector PD Array 3V 2.5V1.5V 1 0V 12 way FR 1 1 Temp Sensing? JTAG? 2 1 2 3 4 3V2.5V 3 5 6 2 4 7 8 5 9 10 3 6 11 12 0V 10 5 LVDS DCM LVDS CLK40 XC2V1000-3000XC2V40AD9218AD8138Opto Rx 6 FRS_OUT FRS_IN ROS_OUT ROS_IN CLOCK DC CNTRL DATA MO_OUT MO_IN DATA OUT 3 N Full Partially Full RESET

2. Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory1 June 2001 Front End Module Layout 9U Envelope - Active Components Opto Rx NGK 45 mm Double Sided Single Sided 130 mm 27 x 27 mm 12 x 12mm 9 x 9 mm 5 x 3 mm 33 x 40 mm FPGA XC2V1000- XC2V3000 FG676 FPGA XC2V40 CS144 ADC AD9218 ST48 DIFF OP-AMP AD9218 RM8 N.B. No Passives Shown 20 1206020

3. Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory1 June 2001 9U Board Layout Front End Envelope 270 mm130 mm 366.7 mm 1 8 45 mm