1. Introduction EE1411 Design Rules

2. EE1412 3D Perspective Polysilicon Aluminum

3. EE1413 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width scalable design rules: lambda parameter absolute dimensions (micron rules)

4. EE1414 CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly Contact To Diffusion Via Well (p,n) Active Area (n+,p+) ColorRepresentation Yellow Green Red Blue Magenta Black Select (p+,n+) Green

5. EE1415 Intra-Layer Design Rules Metal2 4 3

6. EE1416 Transistor Layout

7. EE1417 Vias and Contacts

8. EE1418 Select Layer

9. EE1419 CMOS Inverter Layout

10. EE14110 Layout Editor

11. EE14111 Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.14 um.

12. EE14112 Sticks Diagram 1 3 In Out V DD GND Stick diagram of inverter Dimensionless layout entities Only topology is important Final layout generated by “compaction” program

13. Introduction EE14113 Packaging

14. EE14114 Bonding Techniques

15. EE14115 Package-to-Board Interconnect

16. EE14116 Package Types