1. Application of Silicon-Germanium in the Fabrication of Ultra-shallow Extension Junctions of Sub-100 nm PMOSFETs P. Ranade, H. Takeuchi, W.-H. Lee, V. Subramanian, and T.-J. King IEEE Trans, Electron Devices, vol. 49, pp.1436-1443, Aug. 2002 C.-F. Huang ( 黃靖方 ) 05/26/2004

2. 2 Outline Introduction Si 1-x Ge x /Si Heterojunctions: Electrical and Materials Characterization A ： Ge + Implantation B ： Selective Ge Deposition and Interdiffusion Si 1-x Ge x S/D PMOSFETs Formed By Ge + and B + Implantation Elevated S/D PMOSFETs Formed By Selective Ge Deposition Summary

3. 3 Introduction For scaling of CMOS technology, the short channel performance is of significant consideration. According to the ITRS, bulk-Si CMOS with L g ≤ 50 nm will require ultra-shallow S/D extension junctions. (x j ≤ 30 nm ) Junctions will be heavily-doped to reduce R s (≤ 200Ω/ □ ) and improve I D.

4. 4 ITRS Roadmap Solution ExistSolution are knownNo Known Solutions (2003 ITRS ) Lp HiP + metal target

5. 5 Introduction (continued) Scaling (Improve SCE) Heavily Doped R S ≤ 200Ω/ □ Improve Drive Current Extremely abrupt Ultra-shallow Junctions (X j ≤ 30 nm) Limitations: Solid solubility Diffusion of dopants in Si

6. 6 Introduction (continued) Why PMOS ? Higher diffusivity Lower solid solubility of B in Si (as compared to As and P) More Challenging This paper discusses two simple approaches to incorporate Ge in the S/D regions which greatly improve the SCE.

7. 7 Techniques to Fabricate Ultra-shallow Junctions Ion implantation with ultralow energy Typical kinetic energy: 10~30 keV Ultralow energy: ≤ 1 keV Disadvantages: High concentration of dopant atoms is achievable, but it is difficult to achieve a high concentration of electrically active dopants.

8. 8 Spike and laser annealing to achieve abrupt junctions With very high active dopant concentrations. Disadvantages: Rely on extremely high temperatures. (near melting) Thermal instability in the gate. (Replacement of high-K dielectrics constrains on max. annealing temp. The excess, super-saturated dopants inactive clusters ) Techniques to Fabricate Ultra-shallow Junctions

9. 9 Outline Introduction Si 1-x Ge x /Si Heterojunctions: Electrical and Materials Characterization A ： Ge + Implantation B ： Selective Ge Deposition and Interdiffusion Si 1-x Ge x S/D PMOSFETs Formed By Ge + and B + Implantation Elevated S/D PMOSFETs Formed By Selective Ge Deposition Summary

10. 10 1.LOCOS isolation 2.Thermal oxidation (~6 nm SiO 2 ) 3.Ge + implantation (6 keV, 1e16 cm -2 ) 4.Annealing 5.Thin Si 1-x Ge x layer was produced (~25 nm) 6.B implantation (5 keV, 3e15 cm -2 ) Fabrication sequence of p+/n Si 1-x Ge x /Si junction diodes A ： Ge + Implantation

11. 11 SIMS Concentration-depth Profiles (Annealing at 900 o C) Peak Ge concentration of ~14% At the surface, a steep profile and a high peak concentration of B are obtained. (5x10 20 cm -3 ) The B profile is markedly shallower with the Ge present

12. 12 Comparison of Leakage Currents for Heterojunction and Control Devices The excess leakage is due to residual physical damage produced by Ge implant. The leakage can be minimized via C implantation into SiGe. The sheet resistance: p+ Si 1-x Ge x 376 Ω/ □ p+ Si layer 2826 Ω/ □ Significant reduction !!

13. 13 B ： Selective Ge Deposition and Interdiffusion 1.Thin poly-crystalline films of Ge (60 nm) were selectively deposited. 2.Boron was implanted into the Ge film. 3.Co-diffusion to form hetero- junction diodes. Fabrication sequence of doped Si 1-x Ge x /Si heterojunction diodes

14. 14 Comparison of SIMS Profiles Indicating Interdiffusion Across Si/Ge Interfaces Interdiffusion between Si and Ge is significantly enhanced Undoped Ge/Si interfaces

15. 15 The B profile is contained within the Ge profile in-situ formation of a heavily doped junction. SIMS Profiles Indicating Interdiffusion Across Si/Ge Interfaces Selective Ge deposition followed by the co-diffusion of Ge and B atoms can lead to the formation of shallow and highly doped Si 1-x /Ge x heterojunction

16. 16 Comparison of Leakage Currents for Heterojunction and Control Devices The higher leakage seen in heterojunction diodes is due to higher density of defects around the Si 1-x Ge x /Si interface. It can be reduced by optimization of implantation and annealing conditions. The sheet resistance: heterojunction 350 Ω/ □ (1min) 300 Ω/ □ (2min) homojunction 748 Ω/ □ (1min)

17. 17 Outline Introduction Si 1-x Ge x /Si Heterojunctions: Electrical and Materials Characterization A ： Ge + Implantation B ： Selective Ge Deposition and Interdiffusion Si 1-x Ge x S/D PMOSFETs Formed By Ge + and B + Implantation Elevated S/D PMOSFETs Formed By Selective Ge Deposition Summary

18. 18 Si 1-x Ge x S/D PMOSFETs Formed By Ge + and B + Implantation 1.LOCOS isolation 2.High-energy implantation to form a retrograde cannel doping profile. 3.To grow 2.5 nm gate oxide and 150 nm undoped poly-Si. 4.E-beam lithography 5.Ge implantation (10 keV, 1x10 16 cm -2 ) (R p =6 nm,ΔR p =4 nm, peak=20%) 6.Annealing to recrystallize 7.Dummy sidewall spacers 8.B implantation (5keV, 3x10 15 cm -2 ) 9.Spacer was removed by H 2 O 2 10.RTA Process Sequence:

19. 19 SiGe layer as sink for diffusing B atoms to form very shallow extensions Si 1-x Ge x S/D PMOSFETs Formed By Ge + and B + Implantation The S/D extensions were formed purely by lateral diffusion of B during the RTA steps The Control device (w/o Ge implant) received an additional LDD B implant (BF 2 + at 5 keV, 3x10 15 cm -2 )

20. 20 Comparison of Short-channel Characteristics of PMOSFETs Short-channel effects are effectively suppressed with the proposed Ge implant process, indicating that more abrupt and shallow junctions are achieved.

21. 21 Comparison of I-V Characteristics The drive current was enhanced compared with the device fabricated by the conventional LDD process DIBL effect reduces significantly!!

22. 22 Outline Introduction Si 1-x Ge x /Si Heterojunctions: Electrical and Materials Characterization A ： Ge + Implantation B ： Selective Ge Deposition and Interdiffusion Si 1-x Ge x S/D PMOSFETs Formed By Ge + and B + Implantation Elevated S/D PMOSFETs Formed By Selective Ge Deposition Summary

23. 23 Elevated S/D PMOSFETs Formed By Selective Ge Deposition 1.LOCOS isolation 2.High-energy implantation to form a retrograde cannel doping profile. 3.To grow 2 nm gate oxide and 150 nm undoped poly-Si 0.8 Ge 0.2. 4.20 nm SiO 2 deposition (hard mask) 5.E-beam lithography & RIE 6.25 nm wide sidewall spacers formed 7.HF dip and 60 nm of Ge selectively implanted (LPCVD) 8.20 nm capping layer of SiO 2 deposition. 9.B + implantation (5keV, 6x10 15 cm -2 ) 10.RTA (900 o C, 7min) 11.Ge and B co-diffusion into Si to from S/D extensions during the annealing steps. Process Sequence:

24. 24 I-V Characteristics (turn-off state) L g =80 nm w/o halo implant Elevated S/D structure Low subthreshold swing (82 mV/decade) L g =60 nm w/ halo implant Elevated S/D structure Acceptable short channel performance (84 mV/decade)

25. 25 Comparison of Short-channel Characteristics of PMOSFETs Elevated S/D structure with Si 1-x Ge x S/D extensions effectively suppresses SCE Drive current: Control device: 178μA/ μm Elevated S/D: 128μA/ μm 40% Improvement!!

26. 26 Outline Introduction Si 1-x Ge x /Si Heterojunctions: Electrical and Materials Characterization A ： Ge + Implantation B ： Selective Ge Deposition and Interdiffusion Si 1-x Ge x S/D PMOSFETs Formed By Ge + and B + Implantation Elevated S/D PMOSFETs Formed By Selective Ge Deposition Summary

27. 27 Summary This work reports on the potential applications of Si 1-x Ge x in the fabrication of ultra-shallow S/D extensions in PMOSFET devices. It is shown to result in excellent suppression of short channel effects. Si 1-x Ge x allows for the fabrication with high concentrations of electrically active dopant atoms and low sheet resistance.

28. 28 Summary Relatively low annealing temperatures is advantageous for integration of high-k dielectrics and metal gate electrodes. These techniques can enable the scaling into the sub-50 nm gate length regimes