1. Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald Graham CSE Dept., University of California, San Diego, CA Character Design and Stamp Algorithms for Character Projection Electron-Beam Lithography

2. Outline Introduction Problem Formulation Character Design for Wire Layouts Character Design and Stencil Compaction for Via Layouts Experimental Results Conclusion

3. Introduction Electron Beam Lithography (EBL) Variable Shaped Beam (VSB) a set of variant rectangles to assemble the layout Character Projection (CP) a limited number of characters on a stencil still constrains the improvement of throughput

4. Problem Formulation (1) Design a limited set of characters and put them in a stencil (2) Match the characters against the layout with smaller number of shots

5. Problems for Wire Layout Implementation wire layout is partitioned into blocks with size cx × cy objective is to design a set of characters with size cx × cy Since the wire layout is generally dense, we assume different characters do not share the same area in the stencil ux, uy to denote the pitches (unit distances) L = cx / ux and H = cy / uy as the number of wires in vertical and horizontal directions in a block

6. Problems for Wire Layout Implementation We have the following assumptions on the capability of CP technology when characters are stamped to the layout: (1) A type of character can be used multiple times (2) Arbitrary position can be chosen for a character to be stamped on the layout (3) A character can be masked so that only a rectangular window of it is exposed (4) The same area of the wire layout can be stamped for multiple times which corresponds to an "OR" operation

7. An example for "stamp" process

8. Problems for Via Layout Implementation objective is to design a set of characters with size c x × c y assume that the via layout has the same block size and pitches in each layer the via layout is generally sparse, several characters may share the same area in the stencil S x ×S y grids with unit size u x ×u y

9. Problems for Via Layout Implementation an example that three characters are compacted into a stencil with much smaller size than the total size of the characters

10. Character Design for Wire Layouts N1: There is a single wire and the segment in the block above is not empty. We extend the wire to fill the block except the top grid. N2: There is a single wire and the segment in the block above is empty. We extend the wire to fill the block. N3: There are two wires and the segment in the block above is empty. First we extend the two wires so that they touch the top and bottom boundary respectively. Then we extend both two wires so that the split between them shrinks to a single grid. The grid position is chosen from a prescribed set Sg whose size is determined by available types of characters.We choose Sg to be a set of grids with fixed distance between neighbors in our experiments. If grids in the split and Sg are disjoint, we reduce the split into an arbitrary grid in it. Others: The layout remains unchanged. We implement the segment using VSB

11. Normalization of the wire layout

12. Character Design for Wire Layouts Type 1: Containing a single empty grid whose position belongs to S g. Type 2: Containing a single empty grid on the top. Type 3: Containing only one wire and no empty grids. Type 4: Containing more than two wires or a single empty grid whose position is not in Sg.

13. Character Design for Wire Layouts normalized segments Type 1: around 4% Type 2 & Type 3: around 95% Type 4: around 1% the total number of different types of characters is

14. Character Design for Wire Layouts greedy algorithm to match characters with the layout

15. Character Design for Wire Layouts In order to achieve a balance between the overhead and the stamp performance, we split the wire layout into rows with different heights less than c y by a dynamic programming algorithm. OPT(h) = c 1 ×overhead − c 2 ×performance

16. Character Design and Stencil Compaction for Via Layouts the vias distributed randomly and sparsely in the layout In order to limit the number of different characters, we restrict that all paths walk in top-right direction Therefore, the number of different characters with path length k or less is

17. Character Design and Stencil Compaction for Via Layouts In order to compact all characters with path length three into a stencil with limited area, we first place multiple off diagonal lines with different gaps w = 1, 2,..., L + H − 2 We call an area between two adjacent off-diagonal lines as a belt.

18. Character Design and Stencil Compaction for Via Layouts

19. finding a permutation σ of 1, 2,...,w to Minimal Traveling Salesman Problem (TSP)

20. Implement the layout construct a directed acyclic graph G(V,E) where the vertex set V contains all vias and an edge (u, v) ∈ E if and only if via v is in the first quadrant of u the bounding box of u and v can be contained in the rectangle L × H. Vertex disjoint path cover of graph G Minmum path cover P* of G For each path in P*, we greedily split it into paths satisfying: (1) the length of them is three or less (2) the bounding box of them can be contained in a character.

21. Wire Layout Experimental Results

25. Via Layout Experimental Results

26. Conclusion Character design stencil compaction and layout matching algorithms for both wire and via layout For the wire layout, we normalize the wires by dummy fills to alleviate the chaotic structure and design characters accordingly For the via layout, we compact a large amount of characters onto a stencil and devise a path cover algorithm to realize the layout. Experimental results show that our framework can greatly improve the throughput of manufacturing over VSB.