1. Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 26: October 31, 2014 Synchronous Circuits

2. Today Managing Timing Reusing Circuits Latches Registers, clocking Penn ESE370 Fall2014 -- DeHon 2

3. Preclass 1, 2 Worst-case delay to output? Shortest delay to output? Penn ESE370 Fall2014 -- DeHon 3

4. Preclass 3 New set of inputs every 20T bit –How does it behave? Penn ESE370 Fall2014 -- DeHon 4

5. Preclass 3 When does Carry In reach bit 17 of final adder? After insertion of new input at 20T bit, how early can A or B input to final adder change Penn ESE370 Fall2014 -- DeHon 5

6. Challenge Logic paths have different delays –E.g. different output bits in an adder Delay of signal data dependent –E.g. length of carry Delay is chip dependent –E.g. Threshold Variation Delay is environment dependent –E.g. Temperature Penn ESE370 Fall2014 -- DeHon 6

7. Challenge Logic paths have different delays Delay of signal data dependent Delay is chip dependent Delay is environment dependent Proper behavior depends on inputs being coordinated –Match the inputs that should interact Penn ESE370 Fall2014 -- DeHon 7

8. Logic Reuse How do we fix this? –Make it possible to input a new value every 20T bit ? Penn ESE370 Fall2014 -- DeHon 8

9. Discipline Add circuit elements to –hold values –and change at coordinated point Control when changes seen by circuit Only have to make sure to wait long enough for all results Decouple –timing of signal change –from timing of signal usage Penn ESE370 Fall2014 -- DeHon 9

10. Latch  =1  Out=/In  =0  Out=Out  transitions 0  1 Out holds value How would a latch help us here? Penn ESE370 Fall2014 -- DeHon 10

11. Synchronous Discipline Add state elements (registers, latches) Compute –From state elements –Through combinational logic –To new values for state elements Penn ESE370 Fall2014 -- DeHon 11

12. Midterm 2 Topics Sizing Tau-model –Estimation and optimization Elmore-delay –Estimation and optimization Energy and power –Estimation and optimization –Dynamic and static Logic –CMOS –Ratioed –Pass transistor Regions of operation Scaling Noise Margins and restoration No clocking –Except to motivate delay targets and power calculations Penn ESE370 Fall2014 -- DeHon 12

13. Latch  =1  Out=/In  =0  Out=Out  transitions 1  0 Out holds value How build latch from CMOS logic? Penn ESE370 Fall2014 -- DeHon 13

14. Latch from Combinational Logic  =1  Out=/In  =0  Out=Out  transitions 1  0 Penn ESE370 Fall2014 -- DeHon 14 1 0 In Out 

15. Latch  =1  Out=/In  =0  Out=Out  transitions 1  0 Out holds value How build latch from pass transistors? –(short hold) Penn ESE370 Fall2014 -- DeHon 15

16. What is the difference? Penn ESE370 Fall2011 -- Mehta & DeHon 16

17. MuxL Level Restorer (“Staticizer”) Penn ESE370 Fall2010 -- DeHon 17

18. Without level restorer Penn ESE370 Fall2010 -- DeHon 18

19. Penn ESE370 Fall2010 -- DeHon 19 With level restorer

20. Level Restore What issue arises here? Penn ESE370 Fall2010 -- DeHon 20

21. Latch with Level Restore Penn ESE370 Fall2011 -- Mehta & DeHon 21

22. Latch  =1  Out=/In  =0  Out=Out  transitions 1  0 Out holds value How build latch from pass transistors? –(long hold) Penn ESE370 Fall2014 -- DeHon 22

23. Static Latch Penn ESE370 Fall2011 -- Mehta & DeHon 23

24. Typical Static Latch Penn ESE370 Fall2011 -- Mehta & DeHon 24 Phi0 /Phi0 Advantages: Static Full Rail Fast Isolation inverters: Input Cap Input/Output Noise State Node Noise

25. Class Ended Here Penn ESE370 Fall2014 -- DeHon 25

26. Latch Timing Issues What timing constraints do latches impose? –When can  change? –How long must  be high? –Delay when  is high? Penn ESE370 Fall2014 -- DeHon 26

27. Shift Register How do you make a shift register out of latches? Penn ESE370 Fall2014 -- DeHon 27

28. Two Phase Non-Overlapping Clocks What happens when  0 is high? What happens when  1 is high? Penn ESE370 Fall2013 -- DeHon 28

29. Two Phase Non-Overlapping Clocks When does the action happen? Penn ESE370 Fall2013 -- DeHon 29

30. Two Phase Non-Overlapping Clocks What could go wrong if the overlap? Penn ESE370 Fall2013 -- DeHon 30

31. Two Phase Non-Overlapping Clocks What timing constraints do we have? Penn ESE370 Fall2013 -- DeHon 31

32. Clocking Discipline Follow discipline of combinational logic broken by registers Compute –From state elements –Through combinational logic –To new values for state elements As long as clock cycle long enough, –Will get correct behavior Penn ESE370 Fall2014 -- DeHon 32

33. Ideas Synchronize circuits –to external events –disciplined reuse of circuitry Leads to clocked circuit discipline –Uses state holding element –Prevents Combinational loops Timing assumptions (More) complex reasoning about all possible timings Penn ESE370 Fall2014 -- DeHon 33

34. Admin Exam Monday –No class at noon – office hour –Exam 7—9pm in Towne 309 Daylight savings time ends Sunday 2am –Get an extra hour to study for exam! (or catchup on sleep) Review Sunday Ketterer –(make sure you account for time change!) Penn ESE370 Fall2014 -- DeHon 34