1. InGaAs/InP DHBTs with Emitter and Base Defined through Electron-beam Lithography for Reduced C cb and Increased RF Cut-off Frequency Evan Lobisser 1,*, Johann C. Rode, Vibhor Jain 2, Han-Wei Chiang, Ashish Baraskar 3, William J. Mitchell, Brian J. Thibeault, Mark J. W. Rodwell Dept. of ECE, University of California, Santa Barbara, CA 93106, USA (Now with 1 Agilent Technologies, Inc., CA, 2 IBM Corporation, VT, 3 GlobalFoundries, NY) Miguel Urteaga Teledyne Scientific & Imaging, Thousand Oaks, CA 91360 Dmitri Loubychev, Andrew Snyder, Ying Wu, Joel M. Fastenau, Amy W. K. Liu IQE Inc., Bethlehem, PA 18015 *evan.lobisser@agilent.com, +1 (707) 577-5629 International Symposium on Compound Semiconductors 2012

2. Outline 2 Motivation HBT Design & Scaling Fabrication Process & Challenge Electrical Measurements Conclusion

3. High gain at microwave frequencies: Precision analog design, high resolution ADCs, DACs Digital logic for optical fiber circuits THz amplifiers for imaging, communications 0.3- 3 THz imaging systems 0.1-1 Tb/s optical fiber links Why THz Transistors? 3

4. Emitter: n ++ InGaAs cap n InP Base: p ++ InGaAs Doping grade Drift collector: n - InGaAs/InAlAs grade n - InP Sub-collector: n ++ InGaAs cap n ++ InP Collector CP Emitter BP Base z X X’ XX’: z Semi-insulating InP substrate C E B Type-I InP DHBTs at UCSB 4

5. Surface prep & doping Lateral scaling Epitaxial scaling ParameterChange collector depletion layer thicknessdecrease 2:1 base thicknessdecrease 1.41:1 emitter junction widthdecrease 4:1 collector junction widthdecrease 4:1 emitter contact resistivitydecrease 4:1 base contact resistivitydecrease 4:1 current densityincrease 4:1 Keep lengths the same, reduce widths 4:1 for thermal considerations To double bandwidth of a mesa DHBT: Keep constant all resistances and currents Reduce 2:1 all capacitances and transport delays HBT Scaling Laws 5

6. T(nm)MaterialDoping (cm -3 )Description 10In 0.53 Ga 0.47 As 8  10 19 : Si Emitter cap 15InP 5  10 19 : Si Emitter 15InP 2  10 18 : Si Emitter 25InGaAs 1-0.5  10 20 : C Base 9.5In 0.53 Ga 0.47 As 1  10 17 : Si Setback 12InGaAs / InAlAs 1  10 17 : Si B-C Grade 3InP 5  10 18 : Si Pulse doping 45.5InP 1  10 17 : Si Collector 7.5InP 1  10 19 : Si Sub Collector 5In 0.53 Ga 0.47 As 4  10 19 : Si Sub Collector 300InP 1  10 19 : Si Sub Collector 3.5In 0.53 Ga 0.47 As UndopedEtch stop SubstrateSI : InP V be = 1.0V, V cb = 0.5V, J e = 0, 27 mA/  m 2 Thin (70 nm) collector for balanced f τ /f max High emitter/base doping for low R ex /R bb Epitaxial Design 6

7. Sub-200 nm Emitter Anatomy 7 TiW W 100 nm Mo High-stress emitters fall off during subsequent lift-offs TiW W Single sputtered metal has non-vertical etch profile Hybrid sputtered metal stack for low-stress, vertical profile W/TiW interfacial discontinuity enables base contact lift-off Interfacial Mo blanket-evaporated for low ρ c SiN x SiNx sidewalls protect emitter contact, prevent emitter-base shorts Semiconductor wet etch undercuts emitter contact Very thin emitter epitaxial layer for minimal undercut

8. Positive i-line lithography Negative e-beam lithography E-beam lithography needed to define < 150 nm emitters and for < 50 nm emitter-base contact misalignment Negative i-line lithography Positive e-beam lithography Lithographic Scaling and Alignment 8 Emitter Base Mesa Base Contact

9. W eb = 155 nm W bc = 140 nm W bc = 150 nm T b + T c = 95 nm TiW W Pt/Ti/Pd/Au SiNx sidewall

10. Measurement 10 RF measurements conducted using Agilent E8361A PNA from 1-67 GHz DC bias and measurements made with Agilent 4155 SPA Off-wafer LRRM calibration, lumped-element pad stripping used to de-embed device S-Parameters Isolated pad structures used to provide clean RF measurements

11. β = 14 for 150 nm junction VB ceo = 2.44 V @ J e = 15 kA/cm 2 R ex ≈ 2 Ω·µm 2 (RF extraction) Collector ρ sheet = 14 Ω/□, ρ c = 12 Ω·µm 2 DC Data 11

12. Peak RF performance at >40 mW/μm 2 Kirk limit not reached RF Data 12

13. Lowest ρ ex to date due to Mo contact, highly doped epi C cb lower than 100 nm collector epi designs due to E-beam litho ρ ex = 2 Ω·μm 2 C cb = 3.0 fF A jc = 1.86 μm 2 ~ 450 nm x 4 μm I c = 12.4 mA V ce = 1.5 V (0.2 S)V be exp -jω(0.23 ps) 13 Equivalent Circuit Model

14. 230 fs 15 fs45 fs τ ec dominated by transit delays, high ideality factor reduces f τ ~ 10% E B 2.5 nm of Pt diffuses ~ 8 nm Expected base ρ c = 4 Ω·μm 2 and R sh = 800 Ω/□ yields f max > 1.0 THz for same f τ Epitaxial design, process damage explain high η b, R bb R sh increased by base contacts reacting with 5 nm (20 %) of base Performance Analysis 14

15. Conclusion 15 E-beam lithography used to define narrow emitter, narrowest base mesa reported to date Narrow mesa, low emitter ρ c enable 33% increase in f max from previous UCSB results with 70 nm collector thickness Epitaxial thinning increased f τ by 10% from 100 nm UCSB designs 1 THz bandwidth possible with improved base contact process This work was supported by the DARPA CMO Contract No. HR0011-09-C-0060. Portions of this work were done in the UCSB nanofabrication facility, part of the NSF-funded NNIN network, and the MRL, supported by the MRSEC Program of the NSF under award No. MR05-20415.

16. Questions?

17. Extra Slides

18. Bipolar Scaling Laws W gap

19. Ti 0.1 W 0.9 SiO x Cr n InGaAs, InP EBL PR Cl 2 /O 2 ICP etch p InGaAs W Ti 0.1 W 0.9 Cr n InGaAs, InP p InGaAs W SiO x High power SF 6 /Ar ICP etch p InGaAs Ti 0.1 W 0.9 Cr n InGaAs, InP W SiO x Low power SF 6 /Ar ICP etch Mo V. Jain Fabrication: Emitter contact 19

20. p InGaAs Ti 0.1 W 0.9 Cr n InGaAs, InP W SiN x PECVD deposition CF 4 /O 2 ICP etch Ti 0.1 W 0.9 W InGaAs wet etch Ti 0.1 W 0.9 W 2 nd SiN x sidewall InP wet etch Fabrication: Emitter mesa 20

21. Base Post Cap C cb,post does not scale with L e  Adversely effects f max as L e ↓  Need to minimize the C cb,post value Undercut below base post No contribution of Base post to C cb

23. Transit time Modulation Causes C cb Modulation Camnitz and Moll, Betser & Ritter, D. Root