1. Overview Why VLSI? Moore’s Law. Why FPGAs? Circuit Component
The system design process

2. Why VLSI? Integration improves the design Integration reduces
lower parasitics = higher speed
lower power
physically smaller
Integration reduces
Manufacturing cost-(almost)
No manual assembly.

3. VLSI and you Microprocessors DRAM/SRAM/flash.
personal computers
Microcontrollers
DRAM/SRAM/flash.
Audio/video and other consumer systems
Telecommunications.

4. Moore’s Law Gordon Moore Predicted that
co-founder of Intel.
Predicted that
Number of transistors per chip would grow exponentially
(double every 18 months)
Exponential improvement in technology is a natural trend
Example : steam engines, dynamos(電動機), automobiles.

5. Moore’s Law plot

6. The cost of fabrication
Current cost
$2-3 billion.
Typical fab line
Occupies about 1 city block
Employs a few hundred people
New fabrication processes
Require 6-8 month turnaround

7. Cost factors in ICs For large-volume ICs For low-volume ICs
packaging is largest cost
testing is second-largest cost
For low-volume ICs
design costs may swamp all manufacturing costs
$10 million-$20 million

8. Mask cost vs. line width

9. Field-programmable gate arrays
FPGAs are programmable logic devices
Logic elements + interconnect.
Provide multi-level logic. LE
Interconnect
network LE LE LE LE LE

10. FPGA design FPGA manufacturer System designer
Creates an FPGA fabric
System designer
Uses the fabric
FPGA fabric design issues
Study sample user designs
Select interconnect topology
Create logic element structures
Design circuits, layout

11. FPGAs and VLSI FPGAs are standard parts VLSI (Custom silicon)
Pre-manufactured
Don’t worry (much) about physical design
VLSI (Custom silicon)
Tailored to your application
Generally lower power consumption and higher speed

12. FPGA vs. VLSI FPGA Pros FPGA Cons Have shorter design cycle
Have no manufacturing delay
Reduce inventory
FPGA Cons
Slower
Larger
More power-hungry.

13. Circuit Component Using Component Representation Hierarchical name
Instantiating
Representation
Net lists
Layout
Stick diagram
Transistor schematic
Mixed schematic

14. Hierarchical name Interior view of a component
Components and wires that make it up
Exterior view of a component
type
body
pins
cout
Full
adder
sum a b
cin

15. Component hierarchy
top i1
xxx i2

16. Hierarchical names
Typical hierarchical name:
top/i1.foo
component
pin

17. Instantiating component types
Each instance has its own name
add1 (type full adder)
add2 (type full adder)
Each instance is a separate copy of the type:
cout
Add1.a
Add2.a
Add2(Full
adder)
Add1(Full
adder)
sum
sum a a b b
cin
cin

18. Net lists and component lists
net1: top.in1 in1.in
net2: i1.out xxx.B
topin1: top.n1 xxx.xin1
topin2: top.n2 xxx.xin2
botin1: top.n3 xxx.xin3
net3: xxx.out i2.in
outnet: i2.out top.out
Component list
top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet
i1: in=net1 out=net2
xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3
i2: in=net3 out=outnet

19. Layout and its abstractions
Layout for dynamic latch:

20. Stick diagram

21. Transistor schematic

22. Mixed schematic
inverter

23. System design Dealing with complexity Top-down vs. bottom-up design
Levels of abstraction

24. The system design process
May be part of larger product design.
Major levels of abstraction
specification;
architecture;
logic design;
circuit design;
layout.
FPGA-based system design

25. Dealing with complexity
Divide-and-conquer
Limit the number of components you deal with at any one time.
Group several components into larger components
transistors form gates
gates form functional units
functional units form processing elements
etc.

26. Top-down vs. bottom-up design
Top-down design
Adds functional detail.
Create lower levels of abstraction from upper levels.
Bottom-up design
creates abstractions from low-level behavior.
Good design
Needs both top-down and bottom-up efforts

27. Design abstractions specification behavior function cost logic circuit
English
Executable
program
Sequential
machines
Logic gates
transistors
rectangles
specification
Throughput,
design time
Function units,
clock cycles
Literals,
logic depth
nanoseconds
microns
behavior
function
cost
register-
transfer
logic
circuit
layout

28. Levels of abstraction Specification Architecture Logic Circuits Layout
function, cost, etc
Architecture
large blocks
Logic
gates + registers
Circuits
transistor sizes for speed, power
Layout
determines parasitics

29. Circuit abstraction
Continuous voltages and time

30. Logic (Digital) abstraction
Discrete levels, discrete time

31. Register-transfer abstraction
Abstract components, abstract data types:
0010 +
0001 +
0011
0100

32. Layout Abstraction Why do we care about layout? Layout determines
Logic delay
Interconnect delay
Energy consumption
For FPGA
We want to understand
FPGA characteristics