1. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Overview n Why VLSI? n Moore’s Law. n The VLSI design process.

2. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Why VLSI? n Integration improves the design: –lower parasitics = higher speed; –lower power; –physically smaller. n Integration reduces manufacturing cost- (almost) no manual assembly.

3. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR VLSI and you n Microprocessors: –personal computers; –microcontrollers. n DRAM/SRAM. n Special-purpose processors.

4. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Moore’s Law n Gordon Moore: co-founder of Intel. n Predicted that number of transistors per chip would grow exponentially (double every 18 months). n Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

5. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Moore’s Law plot

6. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR The cost of fabrication n Current cost: $2-3 billion. n Typical fab line occupies about 1 city block, employs a few hundred people. n Most profitable period is first 18 months-2 years.

7. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Cost factors in ICs n For large-volume ICs: –packaging is largest cost; –testing is second-largest cost. n For low-volume ICs, design costs may swamp all manufacturing costs.

8. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR The VLSI design process n May be part of larger product design. n Major levels of abstraction: –specification; –architecture; –logic design; –circuit design; –layout.

9. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Challenges in VLSI design n Multiple levels of abstraction: transistors to CPUs. n Multiple and conflicting constraints: low cost and high performance are often at odds. n Short design time: Late products are often irrelevant.

10. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Dealing with complexity n Divide-and-conquer: limit the number of components you deal with at any one time. n Group several components into larger components: –transistors form gates; –gates form functional units; –functional units form processing elements; –etc.

11. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Hierarchical name n Interior view of a component: –components and wires that make it up. n Exterior view of a component = type: –body; –pins. Full adder a b cin sum cout

12. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Instantiating component types n Each instance has its own name: –add1 (type full adder) –add2 (type full adder). n Each instance is a separate copy of the type: Add1(Full adder) a b cin sum cout Add2(Full adder) a b cin sum Add1.a Add2.a

13. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR A hierarchical logic design z box1box2x

14. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Net lists and component lists n Net list: net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out n Component list: top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet

15. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Component hierarchy top i1xxxi2

16. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Hierarchical names n Typical hierarchical name: –top/i1.foo component pin

17. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Layout and its abstractions n Layout for dynamic latch:

18. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Stick diagram

19. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Transistor schematic

20. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Mixed schematic inverter

21. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Levels of abstraction n Specification: function, cost, etc. n Architecture: large blocks. n Logic: gates + registers. n Circuits: transistor sizes for speed, power. n Layout: determines parasitics.

22. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Circuit abstraction n Continuous voltages and time:

23. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Digital abstraction n Discrete levels, discrete time:

24. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Register-transfer abstraction n Abstract components, abstract data types: + + 0010 0001 0100 0011

25. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Top-down vs. bottom-up design n Top-down design adds functional detail. –Create lower levels of abstraction from upper levels. n Bottom-up design creates abstractions from low-level behavior. n Good design needs both top-down and bottom-up efforts.

26. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Design abstractions specification behavior register- transfer logic circuit layout English Executable program Sequential machines Logic gates transistors rectangles Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns functioncost

27. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Design validation n Must check at every step that errors haven’t been introduced-the longer an error remains, the more expensive it becomes to remove it. n Forward checking: compare results of less- and more-abstract stages. n Back annotation: copy performance numbers to earlier stages.

28. Modern VLSI Design 3e: Chapter 1 Copyright  1998, 2002 Prentice Hall PTR Manufacturing test n Not the same as design validation: just because the design is right doesn’t mean that every chip coming off the line will be right. n Must quickly check whether manufacturing defects destroy function of chip. n Must also speed-grade.