1. SEMINAR PRESENTATION ON IC FABRICATION PROCESS PREPARED BY: GUIDED BY: VAIBHAV RAJPUT(12BEC102) Dr. USHA MEHTA SOURABH JAIN(12BEC098)

2. CONTENTS LATEST TRENDS IN SEMICONDUCTOR MANUFACTURING 3-D IC FABRICATION IC FABRICATION PROCESS BLOG

3. So far So good! Semiconductor Manufacturing Process 197110 um 2001130 nm 19746 um 200490 nm 19773 um 200665 nm 19821.5 um 200845 nm 19851 um 201032 nm 1989800 nm 201222 nm 1994600 nm 201414 nm 1995350 nm 201610 nm 1997250 nm 20187 nm 1999180 nm 20205 nm

4. DESIGN RULE Some example of DRC's in IC design include: Active to active spacing Well to well spacing Minimum channel length of the transistor Minimum metal width Metal to metal spacing Metal fill density (for processes using CMP) Poly density ESD and I/O rules Antenna effect

5. DIE SHRINK Cedar Mill Pentium 4 processors (from 90 nm CMOS to 65 nm CMOS) Penryn Core 2 processors (from 65 nm CMOS to 45 nm CMOS) Brisbane Athlon 64 X2 processors (from 90 nm SOI to 65 nm SOI) Intel released Clarkdale Core i5 and Core i7 processors fabricated with a 32 nm process, down from a previous 45 nm process used in older iterations of the Nehalem processor microarchitecture.

7. Intel CPU core roadmaps

8. Intel Tick - Tock

9. Architectural change Fabrication proesss MicroarchitectureCodenamesRelease Date TickDie shrink 65 nm P6, NetBurstPresler, Cedar Mill, YonahJanuary 5, 2006 TockNew michroarchitecture core MeromJuly 27, 2006 TickDie shrink 45 nm PenrynNovember 11, 2007 TockNew michroarchitecture Nehalem November 17, 2008 TickDie shrink 32 nm westmereJanuary 4, 2010 TockNew michroarchitecture Sandy Bridge January 9, 2011 TickDie shrink 22 nm Ivy BridgeApril 29, 2012 TockNew michroarchitecture Haswell June 2, 2013 TickDie shrink 14 nm BroadwellSeptember 8, 2014 TockNew michroarchitecture Skylake 2015 TickDie shrink 10 nm Cannonlake2016 TockNew michroarchitecture 2017 TickDie shrink 7 nm 2018 TockNew michroarchitecture 2019 TickDie shrink 5 nm 2020 TockNew michroarchitecture 2021

10. FinFET A double-gate FinFET device. An SOI FinFET MOSFET

11. Tri-gate Transistor Schematic view

13. 3D IC MANUFACTURING TECHNOLOGIES Monolithic Wafer-on-Wafer Die-on-Wafer Die-on-Die

14. BENIFITS OF 3D ICs Footprint Cost Heterogeneous integration Shorter interconnect Power Design Circuit security

16. DISADVANTAGES OF 3D IC MANUFACTURING Higher cost Thinning 2 types of die - master and slave Handling/Align Drill holes/fill plug by metal

17. CHALLENGES FOR 3D IC MANUFACTURING Yield Heat Design complexity Testing Lack of standards Heterogeneous integration supply chain Lack of clearly defined ownership

18. IC FABRICATION PROCESS

19. PROCESSING Deposition Removal Patterning Modification of electrical properties physical vapor deposition (PVD) chemical vapor deposition (CVD) electrochemical deposition (ECD) molecular beam epitaxy (MBE) atomic layer deposition (ALD) etch processes (either wet or dry) chemical-mechanical planarization (CMP) lithography diffusion furnaces ion implantation furnace annealing or rapid thermal annealing (RTA)

20. FRONT-END-OF-LINE PROCESSING FEOL processing refers to the formation of the transistors directly in the silicon

21. Front-end surface engineering is followed by -  Growth of gate dielectric (SiO 2 )  Patterning of the gate  Patterning of the source and drain regions  Implantation od diffusion of dopants to obtain the desired complementary electrical properties

22. BACK-END -OF-LINE PROCESSING Once the various semiconductor devices have been created, they must be interconnected to form the desired electrical circuits. This occurs in a series of wafer processing steps collectively referred to as BEOL

23. WAFER TEST DEVICE TEST DIE PREPARATION PACKAGING

24. HAZARDOUS MATERIALS Poisonous elemental dopants - arsenic, antimony and phosphorus poisonous compounds - arsine, phosphine and silane Highly reactive liquids - hydrogen peroxide, fuming nitric acid and hydrofluoric acid

25. REFERENCES 1) Rajendran, Bipin. "Sequential 3D IC Fabrication – Challenges and Prospects." Chomsky Stanford. Department of Electrical Engineering, Stanford University, n.d. Web. 27 Apr. 2013.. 2) Patti, Robert. "Impact of Wafer-Level 3D Stacking on the Yield of ICs." Future Fab International. Tezzaron Semiconductor, 07 Sept. 2007. Web. 27 Apr. 2013.. 3) "EDA's Big Three Unready for 3D Chip Packaging." EDA's Big Three Unready for 3D Chip Packaging. EE Times, n.d. Web. 27 Apr. 2013. 4) Dally, William J. "Future Directions for On-Chip Interconnection Networks." OCIN Workshop. 7 Dec. 2006. Web. 5) Semiconductor device fabrication - http://en.wikipedia.org/wiki/Semiconductor_device_fabrication 6)3D integrated circuit - http://en.wikipedia.org/wiki/Three-dimensional_integrated_circuit 7)Multigate devices - http://en.wikipedia.org/wiki/Multigate_device

26. THANK YOU