1. 1 Note on Testing for Hardware Components

2. 2 Steps in successful hardware design (basic “process”): 1.Understand the requirements (“product’) 2.Write a complete specification 3.Make a modular design 4.Use incremental implementation 5.Write well-structured, well-commented code 6.Use standard testing strategies, including: design for testability hierarchical testing scan path testing RTL (Register Transfer Level) testing

3. 3 Basic requirements (not hardware-specific)--a testing strategy must be: thorough ongoing DEVELOPED WITH DESIGN (design for testability) note: this implies that several LEVELS of testing will be carried out efficient able to ensure observability of the results of each test applied

4. 4 Where can errors arise in hardware? How can we detect these errors? specification errors design errors fabrication defects physical failures wrong outputs (behavior) timing errors other errors such as “glitches”

5. 5 design errors include: incomplete or inconsistent specifications incorrect mappings between design levels and / or views failure to follow design rules errors made by the designer (“coding errors”) errors due to undiscovered bugs in the design tools

6. 6 fabrication defects include: unwanted shorts or open circuits improper doping mask alignment errors Improvement in the fabrication process can reduce these types of errors and increase the yield (% of good chips per wafer) of the given process

7. 7 physical failures arise from wear on the system and from environmental factors physical faults include fabrication defects and physical failures a physical fault may be permanent, intermittent, or transient for purposes of testing physical faults are usually modeled as logical faults, for example “stuck at 1” or “stuck at 0”

8. 8 testing methods: in this course we will use simulation to “test” our circuits; when results of the simulation are acceptable, the actual circuit can then be tested through downloading onto the board we will mainly be concerned with two types of design errors: behavioral errors (the output values are not what was predicted) timing errors (delay between registers is too long for the correct values to be saved)

9. 9 controllability and observability: in the physical device, we need to be able to 1. control the internal state of each flip-flop and of inputs 2. observe the output values at various points in the circuit we do not have enough I/O pins to access all desired sites directly solution: use scan path testing

10. 10 using a scan path: flip-flop outputs flip-flop inputs normal operation mode: f_i gets input in_i, produces output out_i scan mode: f_i gets input from f_(i+1) (f_3 gets input from scanin) protocol: scan in a vector; perform test; scan out results note: only 3 pins needed (scanin, scanout, one-bit control line) instead of 8 pins (in general, 3 pins instead of 2N pins for N ff’s) f_3f_2f_1f_0 scanout scanin in_3in_1in_2 out_0out_1out_2 out_3 in_0

11. 11 For your homeworks and project--simulation will support logic testing and some timing analysis--for overall chip, this should be verified in the actual circuit 1. Use hierarchical testing; test as you design; use incremental design and testing, with system tests each time a new component is integrated 2. Implement scan path(s) to test register and flip-flop behavior 3. Document your testing through well-commented.vec files