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Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 LECTURE 10: KEEE 4425 WEEK 8 CMOS FABRICATION PROCESS.

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Presentation on theme: "Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 LECTURE 10: KEEE 4425 WEEK 8 CMOS FABRICATION PROCESS."— Presentation transcript:

1 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 LECTURE 10: KEEE 4425 WEEK 8 CMOS FABRICATION PROCESS

2 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Manufacturing Process (Courtesy: Prof. Kenneth Laker, U. Penn)

3 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Process p-p- p+p+ p+p+

4 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 A Modern CMOS Process Dual-Well Trench-Isolated CMOS Process

5 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

6 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

7 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

8 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

9 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

10 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

11 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 CMOS Processing Technology

12 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Latch-up problem

13 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Silicon on insulator(SoI)

14 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Silicon on insulator(SoI)

15 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 oxidation optical mask process step photoresist coatingphotoresist removal (ashing) spin, rinse, dry acid etch photoresist stepper exposure development Typical operations in a single photolithographic cycle (from [Fullman]). Photo-Lithographic Process

16 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Images after Lithography

17 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Patterning of SiO2 Si-substrate (a) Silicon base material (b) After oxidation and deposition of negative photoresist (c) Stepper exposure Photoresist SiO 2 UV-light Patterned optical mask Exposed resist SiO 2 Si-substrate SiO 2 2 (d) After development and etching of resist, chemical or plasma etch of SiO 2 (e) After etching (f) Final result after removal of resist Hardened resist Chemical or plasma etch

18 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Plasma Etch Tool Dry Etching

19 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After Nitride Etch

20 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After Resist Strip

21 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Etching

22 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Etch Wafers in KOH(potassium hydroxide) Wet etching

23 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Single sided KOH Etch Apparatus

24 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After KOH Etch

25 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Deposit Polysilicon

26 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Deposition

27 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After Polysilicon Deposition

28 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Hand Spinner Coat(photoresist coating)

29 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Exposure Tools

30 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Pattern Developing (hand develop)

31 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After photolithography

32 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Picture of Wafer After Polysilicon Etch

33 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Sputter Aluminium

34 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Wafer Saw

35 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Photo cross-section of a transistor

36 Norhayati Soin 05 KEEE 4425 WEEK 8 2/9/2005 Review Questions 1.Described briefly technological steps required to manufacture a CMOS inverter. Clearly specify masks used in each step. Give relevant sketches. 2.Give a brief explanation for the following CMOS process technologies: (i)N-well (ii)P-well (iii)Twin well 3.Why do we need design rules. 4.Contrast the difference between micron rules and scalable rules. Give one advantage for using each design rule type.

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