1. 1 CSCE 932, Spring 2007 Yield Analysis and Product Quality

2. 2 Yield Analysis & Product Quality Yield, defect level, and manufacturing cost Clustered defects and yield model Test data analysis Example: SEMATECH chip Summary

3. 3 Test Performance Test Good/Bad? PASSFAIL Good Bad ALL CHIPS Good Bad Tested As Good Good Tested As Bad Bad (Yield) (Yield Loss) (Overkill) (Y bg ) (Reject Rate or DPM) (Tester Yield) These two items determine the tester performance

4. 4 Reject Rate (DPM) Basics Reject Rate or Defectives per million (DPM) is a measure of product quality Zero DPM can be achieved by: Perfect yield (100% yield => no bad parts) Perfect test (100% coverage => all bad parts eliminated in testing, all good parts passed) Neither fabrication nor testing process is perfect hence non-zero DPM is a fact of life. DPM minimization is an important goal of quality-conscious companies. For commercial VLSI chips a DL greater than 500 dpm is considered unacceptable.

5. 5 Ways to Estimate DPM Field-Return Data Get customers to return all defective parts, then analyze and sort them correctly to estimate DPM DPM Modeling and Validation Analytical approach using yield and test parameters in the model to predict yield. Steps: 1. Develop a model 2. Calibrate it (Determine parameter values) 3. Estimate the DPM 4. Verify against actual measurements 5. Recalibrate in time and for new designs or processes

6. 6 VLSI Chip Yield and Cost Manufacturing Defect: Chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. Good Chip: One without a manufacturing defect. Yield (Y): Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Chip Cost:

7. 7 Clustered VLSI Defects Wafer Defects Faulty chips Good chips Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77

8. 8 Yield Modeling Statistical model, based on distribution of defects on a chip: p(x) = Prob(number of defects on a chip = x) Yield = p(0) Empirical evidence shows that defects are not uniformly randomly distributed but are clustered. A form of negative binomial pdf is found to track well with observed data.

9. 9 Binomial and Negative Binomial pdf Bernoulli trials: A biased coin with success probability = p is tossed repeatedly. Binomial: If the coin is tossed n times what is the probability of x successes? Negative Binomial: What is the probability of x failures occurring before the r-th success?

10. 10 Mathematical Definitions Binomial: Negative Binomial * : * “Negative” comes from the fact the the distribution can also be written as

11. 11 Generalized Negative Binomial Distribution When r is a non-integer, the above interpretation breaks down but the form is useful in modeling count data:

12. 12  For modeling the defect distribution we make the following substitutions in the above eqn: where, d = Defect density = Average number of defects per unit of chip area A = Chip area  = Clustering parameter

13. 13 p(x) = Prob(number of defects on chip =x) Defect Distribution Equation

14. 14 Yield Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad /  )  Example: Ad = 1.0,  = 0.5, Y = 0.58 Unclustered defects:  =, Y = e - Ad Example: Ad = 1.0,  =, Y = 0.37 too pessimistic !  

15. 15 Determination of DL from Test Data (Basic Idea) Combine tester data: #chips passing vs. test-pattern number with the fault coverage data: cum. fault coverage vs. test-pattern number to derive the data: #chips passing vs. fault coverage Extend the defect model to a fault model (yield of chips vs. fault coverage) and determine its parameters by curve fitting.

16. 16 Modified Yield Equation Three parameters: Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter,  Stuck-at fault coverage, T The modified yield equation: Y (T ) = (1 + TAf /  ) -  Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af /  ) - 

17. 17 Defect Level Y (T ) - Y (1) DL (T ) = -------------------- Y (T ) (  + TAf )  = 1 - -------------------- (  + Af )  Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A,  is the fault clustering parameter. Af and  are determined by test data analysis.

18. 18 Example: SEMATECH Chip Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont 116,000 equivalent (2-input NAND) gates 304-pin package, 249 I/O Clock: 40MHz, some parts 50MHz 0.45  CMOS, 3.3V, 9.4mm x 8.8mm area Full scan, 99.79% fault coverage Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock Data obtained courtesy of Phil Nigh (IBM)

19. 19 Test Coverage from Fault Simulator Stuck-at fault coverage Vector number

20. 20 Measured Chip Fallout Vector number Measured chip fallout

21. 21 Model Fitting Y (T ) for Af = 2.1 and  = 0.083 Measured chip fallout Y (1) = 0.7623 Chip fallout and computed 1-Y (T ) Chip fallout vs. fault coverage Stuck-at fault coverage, T

22. 22 Computed DL Stuck-at fault coverage (%) Defect level in ppm 237,700 ppm (Y = 76.23%)

23. 23 Summary VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (  ) Yield drops as chip area increases; low yield means high cost Fault coverage measures the test quality Defect level (DL) or reject ratio is a measure of chip quality DL can be determined by an analysis of test data For high quality: DL < 500 ppm, fault coverage ~ 99%