1. 1 With Insights from: Bill Klein (HPL Linear), Rod Burt (HPL LInear), Bernd Rundel (HPL DAP), Rick Downs (HPL DAP), Bob Benjamin (HPL DAP) Selecting the Right Amplifier for a Precision CDAC SAR A/D Tim Green (HPL Linear)

2. 2 Factors of Concern  Power Supply Rails  Size of LSB  Offset  Drift  Noise  Bandwidth  Distortion  A/D Architecture Target Example: +5V, 16-Bit, 100kHz, CDAC, SAR, A/D Application

3. 3  Single Supply +5V +3.3V +1.8V Signal ranges: +1.5V to +5V Power Supply Rails  Bipolar +/- 15V Implies: +/-10V signals

4. 4  Signal range is critical +/-10V is a 20V range  12 bits: 20V/4,096 = 4.88mV per LSB  16 bits: 20V/65,536 = 305µV per LSB +5V range  12 bits: 5V/4,096 = 1.22mV per LSB  16 bits: 5V/65,536 = 76.2µV per LSB  24 bits: 5V/16,777,216 = 298nV per LSB +3.3V range  12 bits: 3.3V/4,096 = 806µV per LSB  16 bits: 3.3V/65,536 = 50.4µV per LSB  24 bits: 3.3V/16,777,216 = 196nV per LSB LSB Size

5. 5 DC Parameters  If all you have to work with is 38µV (1/2 LSB)… Offset Voltage becomes significant  Offset from differential bias current, too! OPA335 as an example  Single Supply  Input offset less than 20µV  Temperature Changes If your system has to operate from -25°C to +75°C, you have a 100°C range of temperature change. If all you have is 38µV (1/2 LSB)…  And 20 µV is used up by offset, then you have 18 µV allowed for drift, so you can handle 180nV/°C of drift  Note: Offset effect may be compensated in the system software!

6. 6  Noise - depends upon bandwidth Resistor noise  1K ohm resistor = 579nV @ 25°C, 20kHz bandwidth. Current noise Voltage noise Sampling Noise of A/D > Tens of μVolts  Distortion THD+N of a 16-bit converter should be better than -98dB, or 0.0011% - again, over the bandwidth of interest. Suitable op amps:  OPA627(Dual Supply)  OPA350, OPA134 (Single Supply)  Single Supply Op Amps As common mode voltage changes, op amp passes through different regions of bias - this results in something similar to crossover distortion AC Parameters

7. 7 Single Supply RRI Plot - V OS vs CMV OPA2340 (Dual: V OUT1 & V OUT2 from different halves) CMV V OUT1 V OUT2 (Most RRI Op Amps Except OPA363/OPA364) Gain=X100 Diff Amp Configuration CH1 CH3 CH2

8. 8 Single Supply RRI Alternate Avoids CM Input “Crossover”

9. 9 Single Supply Inverting “Buffer”  Z IN is R I (typically 100MΩ range  V OUT of Buffer is Inverted from V IN  V CM does not move and is steady at 1/2V CC  Mismatch in ratios of R F / R I = 1 and R B1 / R B2 = 1 Gain & Offset Errors  R I, R F, R B1, R B2 are additional noise sources

10. 10 Input Buffer Selection  Charge injection causes large spike which must settle in t SAMP.  Adding a capacitor (and possibly a resistor) can reduce spike  Op amp must be capable of charging capacitance in t SAMP to 0.5LSB. Low output impedance at high frequency required.  OPA627 (Dual Supply), OPA350 (Single Supply)

11. 11 What Settling Time?  Think of a linear voltage regulator – There are TWO Settling Times. Line Transient Load Transient

12. 12 What Settling Time?  Similar to Linear Regulator Line Transient = Load Transient = Input Step Voltage; Output Step Voltage; Output Voltage Slew RateOutput Step Current

13. 13 Settling Time

14. 14 Op Amp “Line Transient”  Response to change in input signal  Includes Slew Rate.  Op Amp data sheets MAY address Settling Time to 0.01%  But we need 0.0007629% for a 16 bit system

15. 15 “Load Transient” is WORST  We know the load is the input capacitance of the A/D (C SH )  We do NOT know the starting voltage on C SH. Possible voltages: GND, Mid-Rail, Random  The Op Amp data sheet does NOT even mention “Load Transient” response.

16. 16 System Design Variables Op AmpFilter ADC Noise, Signal BW,Noise Filtering, Acquisition Time, CMV Range, Slew Rate,Cload Isolation, Architecture (CDAC SAR) Output Impedance, Settling Time,Charge Bucket Power Supply, Load Transient, Gain Error, (Flywheel) Data Rate, Resolution, Power Supply, V OS vs CMV Input, ADC Input, ADC Ref In Circuit Topology, THD + Noise

17. 17 SAR A/D < 500kHz  70% Applications Slow Moving “Real World Process” Signals Fast Acquisition & Conversion Allows More System Time For Processing, Computation, Decision Making Multiplexed, Scanning Systems for Slow Moving Signals  30% Applications AC Fast Moving Dynamic Signals “Real Time” Processing of Input Signals  Assume for our analysis that during sample time V IN is constant

18. 18 Analysis By Example

19. 19 Analysis Will Use  Tricks  Data Sheet Parameters  Factory Only Parameters  Rules of Thumb  Testing

20. 20 A/D Converter Terms  Acquisition Time (t SMPL ): The time the internal A/D sample capacitor is connected to the A/D input.  Conversion Time (t CONV ) The additional time the A/D requires to convert the analog input to a digital output after the acquisition time (t SMPL ) is complete.  Throughput Rate [Sampling Rate] Maximum frequency at which A/D conversions can be repeated  i.e. 100kHz Throughput Rate [Sampling Rate] implies that an input analog signal may be converted every 10μs.

21. 21 Standard ADS8320 Timing t SMPL = 4.5 Clk Cycles min

22. 22 A/D t SAMPL Trick System Clock (SCLCK)DCLOCKt SMPL t CONV t power down Throughput Rate 2.4MHzSystem Clock 4.5 SCLKs 1.87  s 16 SCLKs 6.67  s 3.5 SCLKs 1.46  s 100kHz 2.4MHz Modified System Clock for t SMPL = 9 System Clock Cycles 9 SCLKs 3.75  s 16 SCLKs 6.67  s 3.5 SCLKs 1.46  s 84kHz 2x t SAMPL = 84% Throughput Rate

23. 23 ADS8320 Application Specs  “16 Bit, High Speed, 2.7V to +5V, micropower sampling A/D”  V CC = +5V, V REF = +5V  Throughput Rate (Sampling Rate) = 100kHz  DCLOCK = 2.4MHz, t SAMPL =1.88μs  Input Signal = 4.87V PP (65mV to +4.935V range),1kHz max  SNR = 88dB @ 1kHz  THD = -86dB @ 1kHz  SINAD = 84dB @1kHz  SFDR = 86dB  ENOB = 14.33

24. 24 OP Amp Buffer Application Specs  Application: Single Supply = +5V Buffer – NO CM Input Crossover ! Slew Rate to track 1kHz Input Wideband for good gain flatness: 1kHz, G=1 Wideband for fast transient response to Noise Filter Transients Low Noise for 16 Bit performance Fast Settling time for output transients Adequate Output Drive Current for Filter Transients RRIO for 65mV to +4.935V Input and Output on +5V Supply  Best Industry Choice OPA363 or OPA364 (OPA363 with Shutdown feature) “1.8V, 7MHz, 90dB CMRR, Single-Supply, Rail-To-Rail I/O”

25. 25 OPA363/OPA364 Application Specs  SR min (V/μs) = 2 π fV OP (1e-6) Minimum Slew Rate to track input sinewave (@<1% Distortion?) SR min = 2∙ π ∙1kHz∙(4.87Vpp/2)∙(1e-6) = 0.015V/μs OPA363/OPA364 = 5V/μs Choose Op Amp SR > 2 X SR min  Gain Error AV CL = Aol/(1+Aolβ) Aol @1kHz = 80dB = 10000 β = 1 for Unity Gain Follower AV CL = 10,000/(1+10000∙1) = 0.99990001  0.009999% Gain Error @ 1kHz  ≈ 12 Bit (1/2 LSB Accuracy)  Calibrate gain error at system level  Many systems are more concerned about relative changes than absolute  A/D Initial Reference Error (0.02% < Typical Range < 0.2%)  Settling Time OPA363/OPA364: t S = 1.5μs to 0.01%, V S =+5V, G=+1, 4V Step A/D t SAMP = 1.88μs so this looks like a possible good candidate t S to 0.01% < t SAMP

26. 26 OPA363/OPA364 Application Specs  THD+Noise OPA363/OPA364:  THD+N = 0.002%, G=1, R L =2kΩ, V S =5V, f=1kHz, V OUT = 1Vrms 16Bit desired 0.0011%  Open Loop Output Resistance (R O )  OPA363/OPA364: R O = 200Ω  Output Current OPA363/OPA364: I O+ = 40mA,V OUT = +/-0.75V, +/-V S = +/-2.5V OPA363/OPA364: I O- = 40mA,V OUT = +/-0.5V, +/-V S = +/-2.5V OPA363/OPA364: I O+ & I O- = 10mA,V OUT = +/-2.25V, +/-V S = +/-2.5V (continued)

27. 27 Filter Application Specs  R SW = 100Ω (Not needed for Buffer & Filter Calculations)  C SH = 50pF  Worst case ΔV across C SH is V REF V REF = +5V  t SAMPL = 1.88μs

28. 28  Charge Transfer Equation: Q = CV  Charge required to charge C SH to V REF Q SH = C SH V REF Q SH = 50pF∙5V = 250pC  IDEAL C FLT (What does C FLT have to be for 1/2 LSB droop on C FLT to change C SH by V REF ) “Charge Bucket” to fill C SH with only a 38μV (1/2LSB) droop on C FLT Q FLT =Q SH Q FLT = C FLT (38μV) 250pC = C FLT (38μV) → C FLT = 6.6μF  IDEAL C FLT = 6.6μF Not a good, small, cheap high frequency ceramic capacitor Not practical for Op Amp to drive directly (stability, transient current) Isolation resistor likely not large enough to help isolate Cload and still meet necessary filter time constant Filter Application Specs (cont)

29. 29 Filter Application Specs (cont)  Partition the “Charge Bucket” 95% from C FLT 5% from Op Amp  C FLT value required to provide Q SH with <5% droop on C FLT Q FLT = Q SH Q FLT = C FLT (0.05V REF ) 250pC = C FLT (0.05∙5V) → C FLT = 1nF  During t SAMPL the Op Amp must replace 5% V REF on C FLT Ensure C FLT is at least 10X > C SH  This implies dominant load for Op Amp Buffer is C FLT  1nF = 20 X 50pF  C FLT = 20X C SH

30. 30 Filter Application Specs (cont)  Time required for C SH & R SW to settle to 1/2LSB @ 16 Bits R SW = 100Ω (If unknown assume 100 Ω) τ A/D = R SW C SH = 100Ω∙50pF = 5ns t A/D settle = 12 τ A/D = 60ns Small in comparison to t SAMPL  R FLT Calculation t FLT settle = t SAMPL = 12τ FLT  t FLT settle = 1.88μs = 12τ FLT 12τ FLT = 1.88μs → τ FLT = 157ns τ FLT* = 0.60 τ FLT  40% Margin for:  Op Amp Output Load Transient  Op Amp Output Small Signal Settling Time τ FLT* = R FLT C FLT  0.60∙157ns = R FLT 1nF → R FLT =94.2Ω  Use R FLT = 100Ω

31. 31  Op Amp Transient Output Drive to R FLT & C FLT I Opk max = (5% V REF )/(R FLT ) = 250mV/100Ω = 2.5mA  OPA363/OPA364: I O+ & I O- = 2.5mA,V OUT ≈ +/-2.428V, +/-V S = +/-2.5V V S = +5V Single Supply  V OUT = +4.928V Filter Application Specs (cont)

32. 32  Modified Aol due to R FLT & C FLT f PX = 1/[(R O + R FLT )C FLT 2π]  f PX = 1/[(200Ω + 100Ω)1nF∙2π] = 530kHz f ZX = 1/[R FLT C FLT 2π]  f ZX = 1/[100Ω∙1nF∙2π] = 1.6MHz  Stability Check At fcl = 3.2MHz “Rate-of-closure” is 20dB/decade  f ZX cancels f PX before fcl f PX and f ZX are < decade apart  Phase of pole will be cancelled by phase of zero  Buffer Closed Loop Gain Bandwidth fcl = 3.2MHz  V OA BW >2x fcl V OA f -3db = fcl = 3.2MHz V OA BW > 2*fcl = 2*3.2MHz = 6.4MHz OPA364 BW = 7MHz Op Amp + Filter Analysis – Small Signal

33. 33 OP Amp + Filter Analysis – Small Signal (cont)

34. 34 Log Scale Trick Log Scale Trick (f P = ?): 1) Given: L = 1cm; D = 2cm 2) L/D = Log 10 (f P ) 3) f P = Log 10 -1 (L/D) = 10 (L/D) 4) f P = 10 (L/D) = 10 (1cm/2cm) = 3.16 5) Adjust for the decade range working within – 10Hz-100Hz decade  f P = 31.6Hz 6) L = Log 10 (fp’) X D where fp’ = fp normalized to the 1-10 decade range – f P = 31.6  f P ’ = 3.16

35. 35 OP Amp + Filter Analysis – Small Signal (cont)  Small Signal Rise Time (10% to 90%) t r = 0.35 / fcl  t r = 0.35 / 3.2MHz = 0.109µs = 109ns  Small Signal Settling Time Constant τ settle ss = 1/(2πfcl)  τ settle SS = 1/(2π∙3.2MHz) = 49.7ns  Small Signal Settling Time t settle ss = 12τ = (12)(49.7ns) = 596.4ns  Small Signal Transient Response < 40% t SAMPL t tran ss < 40 % t SAMPL  t r + t settle SS < (0.40)(t SAMPL )  109ns + 596.4ns < (0.40)(1.8µs)  705.4ns ? < 720ns  Close enough to proceed Small Signal Transient Response

36. 36 OP AMP + Filter Noise Analysis  Op Amp + Filter BW = 1.6MHz V noise = (Op Amp Noise)[(Filter BW)(Single Pole Noise BW Ratio)] V noise = [17nV/√Hz][√(1.6MHz∙1.57)] = 26.94μVrms  White Noise Dominant with 1.6MHz BW Resistor Noise = √(4KTRB)  B = (Filter BW)(Single Pole Noise BW Ratio) = 1.6MHz∙1.57 = 2.5MHz  KT = 4.11x10 -21 @ 25°C 100Ω noise = √[4(4.11x10 -21 )(100 Ω)(2.5MHz)] = 2.03μVrms → Negligible  A/D Noise SNR A/D = 88dB SNR A/D = 20 Log 10 (V IN rms/V noise rms) V IN = 5V PP = 1.7675Vrms A/D Vnoise = 70.365μVrms  System SNR SNR System = 20Log 10 {[V IN rms] / √[(ADC Vnoise) 2 + (V noise ) 2 ]} SNR System = 20Log 10 {[(4.87Vpp/2)(0.707)] / √[(70.365 μVrms) 2 + (26.94μVrms) 2 ]} SNR System = 87.18dB  ENOB (ideal) = [SNR(dB) – 1.76] / 6.02 ENOB System = [87.18 -1.76] / 6.02 = 14.19

37. 37 ADS8320 On Test System ADS8320 Data Sheet: SNR = 88dB THD = -86dB SINAD = 84dB SFDR = 86dB ENOB = 14.33

38. 38 OPA364, Filter, ADS8320 On Test System Op Amp+Filter+ADS8320 Calculated: SNR = 87.18dB ENOB = 14.19

39. 39 Comparison of Tests ADS8320 OnlyOPA364, Filter, ADS8320 AD8S320 Data Sheet: SNR = 88dB THD = -86dB SINAD = 84 DB SFDR = 86dB ENOB = 14.33 Op Amp+Filter+ADS8320 Calculated: SNR = 87.18dB ENOB = 14.19

40. 40 Reference Buffer Selection  Reference is DC, right? So a slow op amp is OK?  No! Same thing happens on reference input as analog input, but it must settle in 1 clock cycle!  Requirements on reference buffer are even more stringent.  Possible Circuit:

41. 41 Promise of more to come…  This is just the beginning  Tuning for BEST results Filter Capacitor AC Magnitude DC Offset Sample Rate  Different converters  Testing DC parameters  Testing AC parameters  Rules of Thumb & Tricks To Optimize Op Amp, Filter, A/D System  Each Customer WILL NEED TO TEST His/Her Final Application

42. 42 Selecting the Right Amplifier for a Precision CDAC SAR A/D Summary of Procedure

43. 43 Summary Steps - CDAC SAR A/D Input Buffer & Filter Selection

44. 44 Buffer / Filter Selection for CDAC SAR A/D Input 1)Specify System Voltages 2)Define maximum input signal Highest Frequency Largest Voltage Swing 3)Choose A/D Converter Select Number of Bits of Resolution Select Maximum Throughput Rate (Sampling Rate) Select Minimum Acquisition Time (t SAMP )  Use D CLOCK stop trick if longer t SAMP is desired 4)Choose C FILT V REF is max ΔV across C SH Q SH = C SH V REF Q FLT = Q SH Q FLT = C FLT (0.05V REF ) Ensure C FLT is at least 10X > C SH

45. 45 Buffer / Filter Selection for CDAC SAR A/D Input (cont.) 5)Choose R FILT t FLT settle = t SAMPL = (#τ)τ FLT (where #τ is number of time constants to reach 1/2LSB settle – i.e. 12 time constants for settling to ½ LSB for 16Bit A/D) Solve for T FLT τ FLT* = 0.60 τ FLT τ FLT* = R FLT C FLT  Solve for R FLT 6)Calculate Op Amp Transient Output Drive to R FLT & C FLT I Opk max = (5% V REF )/(R FLT ) 7)Calculate Op Amp Unity Gain Bandwidth First pass select unloaded Op Amp UGBW > 2 X V FLT f -3db  V FLT f -3db = 1/[R FLT C FLT 2 π ]

46. 46 Buffer / Filter Selection for CDAC SAR A/D Input (cont.) 8)Op Amp Selection - General Choose Buffer or Inverting Buffer Configuration  If Buffer on Single Supply beware of “Input CMV Crossover” Slew Rate: SR min (V/μs) = 2πfV OP (1e-6)  Choose Op Amp SR > 2 X SR min Gain Error (at the maximum input signal frequency)  AV CL = Aol/(1+Aolβ)  A/D Initial Reference Error (0.02% < Typical Range < 0.2%) Settling Time  t S to 0.01% < t SAMP THD+N  Close to desired ½ LSB chosen Accuracy Op Amp Current Drive [I Opk max = (5% V REF )/(R FLT )]  Choose for V OPK @ I Opk max Unity Gain BW:  First pass select unloaded Op Amp BW > 4 X V FLT f -3db  Output Resistance (R O )  Factory Only Parameter (if not specified in data sheet)

47. 47 Buffer / Filter Selection for CDAC SAR A/D Input (cont.) 9)Op Amp Selection – Small Signal Modify Aol due to R FLT & C FLT  f PX = 1/[(R O + R FLT )C FLT 2 π ]  f ZX = 1/[R FLT C FLT 2 π ] Stability Check  At fcl = 3.2MHz “Rate-of-closure” is 20dB/decade  f ZX cancels f PX before fcl  f PX and f ZX are < decade apart  Phase of pole will be cancelled by phase of zero Buffer Closed Loop Gain Bandwidth = fcl (from modified Aol) V OA BW >2x V FLT BW  V OA f -3db = fcl  V FLT f -3db = 1/[R FLT C FLT 2 π ] Small Signal Transient Response  t tran ss < 40 % t SAMPL  t r + t settle SS < (0.40)(t SAMPL )  τ settle ss = 1/(2 π fcl)  t settle ss = (#τ) X τ settle SS

48. 48 Buffer / Filter Selection for CDAC SAR A/D Input (cont.) 10) Op Amp + Filter Noise V noise = (Op Amp Noise)[(Filter BW)(Single Pole Noise BW Ratio)  Single Pole Noise BW Ratio = 1.57  White Noise Dominant at wide BW Resistor Noise = √(4KTRB)  B = (Filter BW)(Single Pole Noise BW Ratio)  Negligible?  KT = 4.11x10 -21 @ 25°C 11) A/D Noise SNR A/D = 20 Log 10 (V IN rms/V noise rms) Calculate A/D Vnoise 12) System SNR SNR System = 20Log 10 {[V IN rms] / √[(ADC Vnoise) 2 + (V noise ) 2 ]} Calculate SNR System 13) System ENOB = [SNR(dB) – 1.76] / 6.02 Calculate System ENOB 14) Prototype & Test Final Configuration

49. 49 Buffer Op Amp R O (Output Resistance) Part R O (ohms)Part Ro (ohms)Part Ro (ohms) OPA13280OPA348600OPA62755 OPA22740OPA35050OPA68450 OPA27710OPA35344THS450314 OPA30020OPA35435TLC080100 OPA33590OPA35540TLC081100 OPA336250OPA35630TLC2272140 OPA34080OPA363160TLE207180 OPA34380OPA38030TLV2461173

50. 50 An Analysis of an Op Amp’s Open Loop Output Resistance and Closed Loop Output Resistance Appendix - Facts about R O and R OUT

51. 51 Op Amp Model for Derivation of R OUT

52. 52  = V FB /V OUT = [V OUT (R I / {R F + R I })]/V OUT = R I / (R F + R I ) R OUT = V OUT /I OUT V O = -V E Aol V E = V OUT [R I /(R F + R I )] V OUT = V O + I OUT R O V OUT = -V E Aol + I OUT R O V OUT = -V OUT [R I /(R F + R I )] Aol+ I OUT R O V OUT + V OUT [R I /(R F + R I )] Aol = I OUT R O V OUT = I OUT R O / {1+[R I Aol/(R F +R I )]} R OUT = V OUT /I OUT =[I OUT R O / {1+[R I A OL /(R F +R I )]}]/I OUT R OUT = R O / (1+Aol  ) Derivation of R OUT (Closed Loop Output Resistance)

53. 53 OPA353 Specifications R O = 40Ω R OUT (@1MHz, G=10) = 10Ω Aol @1MHz = 29.54dB = x30

54. 54 OPA353 R OUT Calculation R O = 40Ω R OUT (@1MHz, G=10) = 10Ω Aol @10mHz = 29.54dB = x30 V OUT = I OUT R O / {1+[R I Aol/(R F +R I )]}

55. 55 R OUT vs R O  R O does not change when feedback is used to close the loop  Closed loop feedback forces V O to increase/decrease  The increase/decrease in V O appears at V OUT as a reduction in R O  R OUT is the net effect of R O and closed loop feedback controlling V O

56. 56 Op Amp Model for AC Stability Analysis  R O is defined as the Op Amp’s Open Loop Output Resistance  R O is measured at I OUT = 0 Amps, f = 1MHz (use the unloaded R O for AC stability calculations since it will be the largest value which is the worst case for AC stability analysis)  R O is included when calculating  for AC Stability Analysis

57. 57 Further Investigation of R O & Z O For a detailed discussion of R O and Z O refer to: http://www.analogzone.com/acqt0529.pdf Operational Amplifier Stability – Part 7 of 15: When Does R O Become Z O ? Bipolar Output Op Amp – Open Loop Output Impedance  Resistive, R O, within unity gain bandwidth of op amp CMOS RRO Op Amp – Open Loop Output Impedance  Resistive, R O, at high frequencies  Our stability concerns for this technique are at high frequencies  Capacitive, C O, at low frequencies

58. 58 Zero-Crossover Input Topology Excellent THD+N: 0.0006% Excellent CMRR: 100dB Rail-to-rail input: Input 100mV Beyond Supply Rails Low noise: 4.5nV/√Hz Speed: Gain bandwidth: 50MHz Settling time: 300ns to 0.01% Low offset: 200µV 2.2V to 5.5V operation OPA365 Zero-Crossover, RRIO, 50MHz Single Supply Amplifier Excellent signal linearity over entire input common mode range RRIO maximizes input dynamic range with full use of single supply range Speed and THD specs optimized for up to 500ksps unity gain buffer data acquisition OPA365 directly drives single supply ADCs Single Supply Data Acquisition Security & Surveillance Handheld Test and Measurement Active Filters Audio Preamplifiers & Filters Precision signal conditioning 1k Price: $0.95