1. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6

2. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 2 Outline  Concepts of Xilinx FPGA  Xilinx FPGA Architecture  Introduction to ISE  Code Generator  Constraints and Reports  Configuration  Demo and Lab

3. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Concepts of Xilinx FPGA

4. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 4 Electronic Components

5. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 5 FPGA Benefits Full-Custom ICs Cell-Based ICs Gate ArraysFPGA Speed ●●●●● Integration Density ●●●●● High-Volume Device Cost ●● ●● Low-Volume device Cost ●●● Time to Market ●●● Risk Reduction ●● Future Modification ●● Development Tool ●●●●● Educational Purpose ●●

6. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 6 Full Xilinx Design Support

7. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 7 Xilinx Products  CPLDs and FPGAs

8. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Xilinx FPGA Architecture

9. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 9 The Conceptual CPLD Architecture

10. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 10 The Conceptual FPGA Architecture  Field-programmable  Re-programmable  In-circuit design verification  Rapid prototyping  Fast time-to-market  No IC-test & NRE cost  H/W emulation instead of S/W

11. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 11 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (1/6)

12. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 12  Logic and Routing - the CLB tile Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (2/6)

13. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 13 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6)  Two slices in each CLB  Each slice contains 2 LUT, 2 Register and 2 Carry Logic.  Logic and Routing – Simplified CLB Structure

14. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 14 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (3/6)  Logic and Routing – Look-Up Tables (LUTs)  Combinational logic is stored in Look-up Tables (LUTs) in a CLB.  Capacity is limited by number of inputs, not complexity.  Delay through CLB is constant.

15. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 15 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (4/6)  System Interface – Select IO TM  Supports multiple voltage and signal standards simultaneously  Eliminate costly bus transceivers

16. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 16  System Memory – Distributed RAM, Block RAM and External Memory Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (5/6)

17. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 17 Spatran-2/2E, Virtex / Virtex-E FPGA Architecture (6/6)  System clock management - DLLs  Clock Mirror  Multiplication  1 DLL for 2x  Combine 2 DLL for 4x  Division  Selectable division values - 1.5, 2, 2.5, 3, 4, 5, 8, or 16  Phase Shift  0, 90, 180, 270

18. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 18 Spatran-3, VirtexII FPGA Architecture (1/7)

19. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 19 Spatran-3, VirtexII FPGA Architecture (2/7)  Logic and Routing - the CLB tile

20. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 20 Spatran-3, VirtexII FPGA Architecture (3/7)  System Interface – Select IO TM 23 different standards supported !

21. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 21 Spatran-3, VirtexII FPGA Architecture (4/7)  System Memory –External Memory supports DDR memory

22. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 22 Spatran-3, VirtexII FPGA Architecture (5/7)  System clock management – DCMs

23. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 23 Spatran-3, VirtexII FPGA Architecture (6/7)  System clock management – DCMs

24. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 24 Spatran-3, VirtexII FPGA Architecture (7/7)  Embedded multiplexer

25. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 25 VirtexII Pro FPGA Architecture

26. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 26 Programmable Logic Evolution

27. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Introduction to ISE

28. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 28 ISE Philosophy  ISE 6.1i  Future Xilinx devices  Proactive Timing Closure  ECS & HDL Bencher & XST  Platform  Unix: Solaris 2.7/2.8  PC: Win 2000/XP  Service Pack  http://support.xilinx.com  ISE WebPage  http://www.xilinx.com/ise

29. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 29 Design Flow in ISE (1/2)

30. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 30 Design Flow in ISE (2/2)

31. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 31 Introduction to Projection Navigator (1/4)

32. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 32 Introduction to Projection Navigator (2/4)  Source Windows

33. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 33 Introduction to Projection Navigator (3/4)  Processes for current source

34. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 34 Introduction to Projection Navigator (4/4)  Processes for current source

35. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 35 Create New Project

36. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 36 Create New Source

37. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 37 HDL Source File

38. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 38 Text Entry

39. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 39 Language Templates

40. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 40 Synthesis (1/4)  XST

41. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 41 Synthesis (2/4)  XST Flow

42. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 42 Synthesis (3/4)  Synthesis Step

43. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 43 Synthesis (4/4)  RTL view

44. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 44 Implementation (1/8) Translate - Merge multiple design files into a single netlist Map - Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs) Place & Route - Place components onto the chip, connect them, and extract timing data into reports

45. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 45 Implementation (2/8)

46. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 46 Translate Implementation (3/8)

47. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 47 Map Implementation (4/8)

48. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 48 Implementation (5/8)  Map Property  Trim Unconnected Signals  If you check this item, the mapping tool will remove the unconnected wire that let the tracing back become hardly.  Generate Detailed Map Report  If more detailed report is needed, you can check it. (Recommending check it)  Use Guide Design File (.ncd)  You can refer the last mapping solution so that you maybe get better solution.  Use RLOC Constraints  Constraints of CLB (default check).  Pack I/O Registers/Latches into IOBs  If the value chosen Default that pack the register nearby I/O into I/O block. You can also chose only for input or only for output or off.

49. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 49 Place and Route Implementation (6/8)

50. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 50  Place and Route Property (1/2)  Place & Route Effort Level (Overall)  Effort Level means the P&R effect result. Using the Higher get the better solution, but spend more time.  Starting Placer Cost Table (0-100)  Specify a placement initialization value with which to begin P&R attempts. Each subsequent attempt is assigned an incremental value based on the placement initialization value.  Place and Route Mode  Quick means without timing constraints; Route Only and Re-entrant Route mean P&R must have been run at last once to use this option.  Guide File  Include the.ncd file. Implementation (7/8)

51. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 51  Place and Route Property (2/2)  Use Timing Constraints  Include the.ucf file.  Use Bonded I/Os  If it is checked, signals will be connected to I/O pads.  Generate Detailed PAR Report  Check the value to generate a detailed PAR report.  Generate Post-Place & Route Static Timing Report  Check the value to generate post-place & route static timing report.  Generate Post-Place & Route Simulation Model  Check it for generating required simulation files for ModelSim (*.v and *.sdf). Implementation (8/8)

52. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 52 Download (1/2)

53. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 53 Download (2/2)

54. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Code Generator

55. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 55 What are Cores?

56. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 56 Benefits of Using Cores

57. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 57 Invoking the CORE Generator GUI

58. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 58 Xilinx Code Generator System GUI

59. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 59 Core Customize Window

60. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 60 Core Data Sheet

61. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 61 Core Generator Design Flow

62. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 62 Link with CodeGen IP (Verilog)

63. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Constraints and Reports

64. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 64 Topics  Assign Package Pins (PACE)  Assigning Pins  Create Timing Constraints  The PERIOD Constraints  The Pad-to-Pad Constraints  The OFFSET Constraints  The Constraints Editor  Read Report

65. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 65 Constraints GUI (1/2)

66. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 66 Constraints GUI (2/2)

67. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 67 Assign Package Pins (1/6)  Start PACE Editor

68. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 68 Assign Package Pins (2/6)  PACE Editor GUI

69. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 69 Assign Package Pins (3/6)  Method #1 to assign package pins

70. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 70 Assign Package Pins (4/6)  Method #2 to assign package pins

71. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 71 Assign Package Pins (5/6)  Method #3 to assign package pins

72. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 72 Assign Package Pins (6/6)  Method #4 to assign package pins  Use text editor to edit.ucf files  NET is port name  LOC assign pins to specific location

73. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 73 The PERIOD Constraint

74. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 74 The Pad-to-Pad Constraint

75. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 75 The OFFSET Constraint

76. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 76 The Constraint Editor (1/3)

77. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 77 The Constraint Editor (2/3)  Enter PERIOD and Pad-to-Pad Constraint

78. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 78 The Constraint Editor (3/3)  Enter OFFSET Constraint

79. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 79 Read Report (1/12)  Create Report Files

80. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 80 Read Report (2/12)

81. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 81 Read Report (3/12)  Example of MAP Report (1/2)

82. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 82 Read Report (4/12)  Example of MAP Report (2/2)

83. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 83 Read Report (5/12)

84. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 84 Read Report (6/12)  Example of PAR Report (1/2)

85. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 85 Read Report (7/12)  Example of PAR Report (2/2)

86. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 86 Read Report (8/12)

87. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 87 Read Report (9/12)  Example of Timing Report (1/4)

88. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 88 Read Report (10/12)  Example of Timing Report (2/4)

89. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 89 Read Report (11/12)  Example of Timing Report (3/4)

90. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 90 Read Report (11/12)  Example of Timing Report (4/4)

91. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 91 Post-layout Simulation

92. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Configuration

93. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 93 What is configuration?  Process for loading into the FPGA

94. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 94 Configuration Mode (1/4)

95. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 95 Configuration Mode (2/4)  Serial Mode

96. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 96 Configuration Mode (3/4)  SelectMAP Mode

97. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 97 Configuration Mode (4/4)  JTAG or Boundary Scan

98. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 98 IMACT (1/3) Must double clock “Generate Programming File” before programming FPGA

99. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 99 IMACT (2/3)

100. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU pp. 100 IMACT (3/3)