1. Device Research Conference, 2005 Zach Griffith and Mark Rodwell Department of Electrical and Computer Engineering University of California, Santa Barbara, CA, 93106-9560 Xiao-Ming, Dmitri Loubychev, Ying Wu, Joel Fastenau, Amy W.K. Liu 119 Technology Drive, Bethlehem, PA 18015 griffith@ece.ucsb.edu, 805-893-3273, 805-893-3262 fax In 0.53 Ga 0.47 As/InP Type-I DHBTs having 450 GHz f  and 490 GHz f max with C cb / I c  0.38 ps/V

2. ParameterInP/InGaAsSi/SiGebenefit (simplified) collector electron velocity3E7 cm/s1E7 cm/slower  c, higher J base electron diffusivity40 cm 2 /s~2-4 cm 2 /slower  b base sheet resistivity 500 Ohm5000 Ohmlower R bb comparable breakdown fields Consequences, if comparable scaling & parasitic reduction: ~3:1 higher bandwidth at a given scaling generation ~3:1 higher breakdown at a given bandwidth Challenges for InP HBTs: SiGe has much better scaling & parasitic reduction Present efforts in InP HBT research community Development of low-parasitic, highly-scaled, high-yield fabrication processes Why mesa DHBT? Simple way to continue the advance of epitaxial material for improved speed Motivation for InP HBTs

3. High speed HBTs: some standard figures of merit Small signal current gain cut-off frequency (from H 21 )… Power gain cut-off frequency (from U)… Collector capacitance charging time when switching…

4. Fast divider design considerations

5. Scaling Laws, Collector Current Density, C cb charging time Collector Field Collapse (Kirk Effect) Collector Depletion Layer Collapse 0 mA/  m 2 10 mA/  m 2 0 mA/  m 2 10 mA/  m 2 GaAsSb baseInGaAs base Collector capacitance charging time scales linearly with collector thickness if J = J max Collector thickness—150 nm

6.   ex  7  m 2 needed for 200 GHz clock rate ECL delay not well correlated with f  or f max Key Scaling Limit for digital logic  Emitter Resistance Largest delay is charging C cb  J e  10 mA/  m 2 needed for 200 GHz clock rate Voltage drop of emitter resistance becomes excessive R ex I c =  ex J e = (15  m 2 )  (10 mA/  m 2 ) = 150 mV  considerable fraction of  V logic  300 mV Degrades logic noise margin

7. Digital circuits: towards 200 GHz clock rate underlying technology: 400-500 GHz InP transistors 142 GHz latch from NNIN @ UCSB 150 GHz ICs from UCSB/GSC/RSC 200 GHz is the next goal 1.3  m base-collector mesa

8. DC, RF performance—150 nm collector, 30 nm base Average   36, BV CEO = 5.1 V, BV CBO = 5.8 V ( I c = 50  A) Emitter contact (from RF extraction), R cont = 10.1  m 2 Base (from TLM) : R sheet = 564  /sq, R cont = 9.6  m 2 Collector (from TLM) : R sheet = 11.9  /sq, R cont = 5.4  m 2 Griffith et al., IEEE Electron Device Letters, Vol. 26, Jan 2005

9. DC, RF performance—100 nm collector, 30 nm base Average   40, BV CEO = 3.1 V, BV CBO = 3.6 V ( I c = 50  A) Emitter contact (from RF extraction), R cont  7.8  m 2 Base (from TLM) : R sheet = 629  /sq, R cont = 6.2  m 2 Collector (from TLM) : R sheet = 12.9  /sq, R cont = 4.0  m 2 Griffith et al., IPRM, Glasgow, Scotland, May 2005

10. Layer structure -- 120 nm collector, 30 nm base DHBT Thickness (nm)MaterialDoping cm -3 Description 5In 0.85 Ga 0.15 As 5  10 19 : Si Emitter cap ----In x Ga 1-x As > 4  10 19 : Si Emitter cap grading 20In 0.53 Ga 0.47 As 4  10 19 : Si Emitter 80InP 3  10 19 : Si Emitter 10InP 8  10 17 : Si Emitter 40InP 5  10 17 : Si Emitter 30InGaAs 7-4  10 19 : C Base 15In 0.53 Ga 0.47 As 3  10 16 : Si Setback 24InGaAs / InAlAs 3  10 16 : Si B-C Grade 3InP 2.75  10 18 : Si Pulse doping 78InP 3  10 16 : Si Collector 5InP 1  10 19 : Si Sub Collector 6.5In 0.53 Ga 0.47 As 2  10 19 : Si Sub Collector 300InP 2  10 19 : Si Sub Collector SubstrateSI : InP Objective : Determine collector thickness for improved balance of f , f max Simultaneously > 450 GHz Decrease collector doping for increased collector depletion underneath base contact reduce extrinsic C cb Thin InGaAs sub-collector contact layer from 8.5 nm  6.5 nm for reduced  JA V be = 0.9 V, V cb = 0.0 V

11. DC characteristics—Common emitter and Gummel Summary of device parameters— Average   40, BV CEO = 3.9 V, BV CBO = 4.1 V ( I c = 50  A) Emitter contact (from RF extraction),  cont = 8.4  m 2 Base (from TLM) : R sheet = 610  /sq,  cont = 4.6  m 2 Collector (from TLM) : R sheet = 12.1  /sq,  cont = 8.4  m 2

12. Experimental Measurement of Temperature Rise Temperature rise calculated by measuring I C,  V CB and  V BE …thermal feedback coefficient  = 8.35  10 -4 V/K at J e = 5.8 mA/  m 2  JA = 2.6561 + 1.0878  V cb

13. Microwave gains—peak f  and f max

14. Small signal model—150 nm vs 120 nm collector I c = 22.5 mA V cb = 0.6 V A je = 2.58  m 2 f  = 450 GHz f max = 490 GHz Device junction dimensions: 0.6  m emitter, 4.3  m length, 1.2  m base mesa width  ex  8.4  m 2  c,base  4.6  m 2 I c = 13.2 mA V cb = 0.6 V A je = 2.58  m 2 f  = 391 GHz f max = 505 GHz  ex  10.1  m 2  c,base  9.6  m 2

15. C cb variance of HBTs within CML static divider circuit CML switching endpoints labeled

16. Summary of published HBT performance Collector thickness cited