2. 2 Systems Architecture, Fifth Edition Chapter Goals Describe the system bus and bus protocol Describe how the CPU and bus interact with peripheral devices Describe the purpose and function of device controllers Describe how interrupt processing coordinates the CPU with secondary storage and I/O devices

3. 3 Systems Architecture, Fifth Edition Chapter Goals (continued) Describe how buffers, caches, and data compression improve computer system performance

4. 4 Systems Architecture, Fifth Edition

5. 5 System Bus Connects CPU with main memory and peripheral devices Set of data lines, control lines, and status lines Bus protocol –Number and use of lines –Procedures for controlling access to the bus Subsets of bus lines: data bus, address bus, control bus

6. 6 Systems Architecture, Fifth Edition

7. 7 Bus Clock and Data Transfer Rate Bus clock pulse –Common timing reference for all attached devices –Frequency measured in MHz Bus cycle –Time interval from one clock pulse to the next Data transfer rate –Measure of communication capacity –Bus capacity = data transfer unit x clock rate

8. 8 Systems Architecture, Fifth Edition Bus Protocol Governs format, content, timing of data, memory addresses, and control messages sent across bus Approaches for access control –Master-slave approach –Peer-to-peer approach Approaches for transferring data without CPU –Direct memory access (DMA) –Peer-to-peer buses

9. 9 Systems Architecture, Fifth Edition Logical and Physical Access I/O port –Communication pathway from CPU to peripheral device –Usually a memory address that can be read/written by the CPU and a single peripheral device –Also a logical abstraction that enables CPU and bus to interact with each peripheral device as if the device were a storage device with linear address space

10. 10 Systems Architecture, Fifth Edition Physical access: System bus is usually physically implemented on a large printed circuit board with attachment points for devices.

11. 11 Systems Architecture, Fifth Edition Logical access: The device, or its controller, translates linear sector address into corresponding physical sector location on a specific track and platter.

12. 12 Systems Architecture, Fifth Edition Device Controllers Implement the bus interface and access protocols Translate logical addresses into physical addresses Enable several devices to share access to a bus connection

13. 13 Systems Architecture, Fifth Edition

14. 14 Systems Architecture, Fifth Edition Mainframe Channels Advanced type of device controller used in mainframe controllers Compared with device controllers: –Greater data transfer capacity –Larger maximum number of attached peripheral devices –Greater variability in types of devices that can be controlled

15. 15 Systems Architecture, Fifth Edition SCSI (Small Computer System Interface) Family of standard buses designed primarily for secondary storage devices Implements both a low-level physical I/O protocol and a high-level logical device control protocol

16. 16 Systems Architecture, Fifth Edition

17. 17 Systems Architecture, Fifth Edition

18. 18 Systems Architecture, Fifth Edition Desirable Characteristics of a SCSI Bus Non-proprietary standard High data transfer rate Peer-to-peer capability High-level (logical) data access commands Multiple command execution Interleaved command execution

19. 19 Systems Architecture, Fifth Edition Secondary storage and I/O devices have slower data transfer rates than the CPU.

20. 20 Systems Architecture, Fifth Edition Interrupt Processing Used by application programs to coordinate data transfers to/from peripherals, notify CPU of errors, and call operating system service programs When interrupt is detected, executing program is suspended; pushes current register values onto the stack and transfers control to an interrupt handler When interrupt handler finishes executing, the stack is popped and suspended process resumes from point of interruption

21. 21 Systems Architecture, Fifth Edition Multiple Interrupts Categories of interrupts –I/O event –Error condition –Service request

22. 22 Systems Architecture, Fifth Edition

23. 23 Systems Architecture, Fifth Edition Buffers and Caches Improve overall computer system performance by employing RAM to overcome mismatches in data transfer rate and data transfer unit size

24. 24 Systems Architecture, Fifth Edition Buffers Small storage areas (usually DRAM or SRAM) that hold data in transit from one device to another Use interrupts to enable devices with different data transfer rates and unit sizes to efficiently coordinate data transfer Buffer overflow

25. 25 Systems Architecture, Fifth Edition

26. 26 Systems Architecture, Fifth Edition Computer system performance improves dramatically with larger buffer.

27. 27 Systems Architecture, Fifth Edition Diminishing Returns When multiple resources are required to produce something useful, adding more and more of a single resource produces fewer and fewer benefits Applicable to buffer size

28. 28 Systems Architecture, Fifth Edition Law of diminishing returns affects both bus and CPU performance

29. 29 Systems Architecture, Fifth Edition Cache Differs from buffer: –Data content not automatically removed as used –Used for bidirectional data –Used only for storage device accesses –Usually much larger –Content must be managed intelligently Achieves performance improvements differently for read and write accesses

30. 30 Systems Architecture, Fifth Edition Write access: Sending confirmation (2) before data is written to secondary storage device (3) can improve program performance; program can immediately proceed with other processing tasks.

31. 31 Systems Architecture, Fifth Edition Read accesses are routed to cache (1). If data is already in cache, it is accessed from there (2). If data is not in cache, it must be read from the storage device (3). Performance improvement realized only if requested data is already waiting in cache.

32. 32 Systems Architecture, Fifth Edition Cache Controller Processor that manages cache content Guesses what data will be requested; loads it from storage device into cache before it is requested Can be implemented in –A storage device storage controller or communication channel –Operating system

33. 33 Systems Architecture, Fifth Edition Cache Primary storage cacheSecondary storage cache Can limit wait states by using SRAM cached between CPU and SDRAM primary storage Level one (L1): within CPU Level two (L2): on-chip Level three (L3): off-chip Gives frequently accessed files higher priority for cache retention Uses read-ahead caching for files that are read sequentially Gives files opened for random access lower priority for cache retention

34. 34 Systems Architecture, Fifth Edition Intel Itanium ® 2 microprocessor uses three levels of primary storage caching.

35. 35 Systems Architecture, Fifth Edition Processing Parallelism Increases computer system computational capacity; breaks problems into pieces and solves each piece in parallel with separate CPUs Techniques –Multicore processors –Multi-CPU architecture –Clustering

36. 36 Systems Architecture, Fifth Edition Multicore Processors Include multiple CPUs and shared memory cache in a single microchip Typically share memory cache, memory interface, and off-chip I/O circuitry among the cores Reduce total transistor count and cost and provide synergistic benefits

37. 37 Systems Architecture, Fifth Edition

38. 38 Systems Architecture, Fifth Edition Multi-CPU Architecture Employs multiple single or multicore processors sharing main memory and the system bus within a single motherboard or computer system Common in midrange computers, mainframe computers, and supercomputers Cost-effective for –Single system that executes many different application programs and services –Workstations

39. 39 Systems Architecture, Fifth Edition Scaling Up Increasing processing by using larger and more powerful computers Used to be most cost-effective Still cost-effective when maximal computer power is required and flexibility is not as important

40. 40 Systems Architecture, Fifth Edition Scaling Out Partitioning processing among multiple systems Speed of communication networks; diminished relative performance penalty Economies of scale have lowered costs Distributed organizational structures emphasize flexibility Improved software for managing multiprocessor configurations

41. 41 Systems Architecture, Fifth Edition High-Performance Clustering Connects separate computer systems with high- speed interconnections Used for the largest computational problems (e.g., modeling three-dimensional physical phenomena)

42. 42 Systems Architecture, Fifth Edition Partitioning the problem to match the cluster architecture ensures that most data exchange traverses high-speed paths.

43. 43 Systems Architecture, Fifth Edition Compression Reduces number of bits required to encode a data set or stream Effectively increases capacity of a communication channel or storage device Requires increased processing resources to implement compression/decompression algorithms while reducing resources needed for data storage and/or communication

44. 44 Systems Architecture, Fifth Edition Compression Algorithms Vary in: –Type(s) of data for which they are best suited –Whether information is lost during compression –Amount by which data is compressed –Computational complexity Lossless versus lossy compression

45. 45 Systems Architecture, Fifth Edition Compression can be used to reduce disk storage requirements (a) or to increase communication channel capacity (b).

46. 46 Systems Architecture, Fifth Edition MPEG standards address recording and encoding formats for both images and sound.

47. 47 Systems Architecture, Fifth Edition Summary How the CPU uses the system bus and device controllers to communicate with secondary storage and input/output devices Hardware and software techniques for improving data efficiency, and thus, overall computer system performance: bus protocols, interrupt processing, buffering, caching, and compression