1. 001-96748Owner: ABVY (SKRG, OHP, DCN, GHR, DSG, GMRL, JMY) Synchronous SRAM With On-Chip ECC Quick Presentation Rev **Tech Lead: SKRG 1 High-Performance, Low-Power Synchronous SRAMs With On-Chip ECC to Improve Reliability 1,000x Quick Presentation: Synchronous SRAM With On-Chip ECC ECC = Error-Correcting Code Title

2. 001-96748 Owner: ABVYSynchronous SRAM With On-Chip ECC Quick Presentation Rev** Tech Lead: SKRG 2 Cypress: No. 1 in Flash, SRAM, NVRAM Comparison of Competitors’ Memory Product Portfolios Product CategoryCypress Competitors Performance AdvantageMetrics RenesasISSIMicronToshibaWinbondMacronixFujitsu No. 1 NOR Flash HyperFlash™  Highest read bandwidth333 MBps Serial NOR Flash Highest read bandwidth Fastest program/erase 160 MBps Parallel NOR Flash Highest read bandwidth Fastest program/erase 90 MBps No. 1 SRAM QDR ® -IV Synchronous SRAM  Highest RTR (random transaction rate) 2.1 GT/s Asynchronous SRAM with ECC 1  Highest reliability<0.1 FIT 2 MicroPower™ SRAM Lowest standby current1.5 µA NAND 3 Flash SLC NAND Flash Fastest access time25 ns e.MMC NAND Flash Highest reliability0 FIT 2 No. 1 NVRAM Serial F-RAM™ 4  Lowest standby current100 µA Parallel nvSRAM 5  Fastest NVRAM 6 20 ns AGIGARAM ® 7 Highest-density NVRAM 6 16GB Cypress has the broadest portfolio of high-performance memories for embedded systems 1 Error-correcting code 2 Failures In Time (billion hours) 3 A type of flash memory that offers extremely high densities, low cost and sequential reads 4 Ferroelectric RAM 5 Nonvolatile SRAM 6 Nonvolatile memory that provides direct access to read and write to any memory location in any random order 7 A Cypress brand name Market Positioning

3. 001-96748 Owner: ABVYSynchronous SRAM With On-Chip ECC Quick Presentation Rev** Tech Lead: SKRG 3 Standard Sync and NoBL ® Standard Sync and NoBL ® with ECC 2 QDR ® -II/ DDR-II QDR-II+/ DDR-II+ QDR-II+X/ DDR-II+X QDR-IV Max RTR 1 : 250 MT/s Max BW: 18 Gbps Latency: 1 Cycle Flow-through and Pipeline Modes Max RTR 1 : 250 MT/s Max BW: 18 Gbps Latency: 1 Cycle Flow-through and Pipeline Modes Max RTR 1 : 666 MT/s Max BW: 47.9 Gbps Latency: 1.5 Cycles CIO 3 and SIO 4 Max RTR 1 : 666 MT/s Max BW: 79.2 Gbps Latency: 2 or 2.5 Cycles CIO 3 and SIO 4, ODT 5 Max RTR 1 : 900 MT/s Max BW: 91.1 Gbps Latency: 2.5 Cycles SIO 4, ODT 5 Max RTR 1 : 2.1 GT/s Max BW: 153.5 Gbps Latency: 5 or 8 Cycles Dual-Port Bidirectional ODT 5 Synchronous SRAM Portfolio High Random Transaction Rate (RTR) 1 | Low Latency | High Bandwidth Density 1 Rate of truly random accesses to memory, expressed in transactions per second (MT/s, GT/s) 2 Error-correcting code 3 Common I/O 4 Separate I/O 5 On-die termination; parts are CY7C2x 6 Radiation hardened, military grade 7 AEC-Q100 -40ºC to +125ºC ProductionDevelopment QQYY Availability Sampling Concept Status CY7C41xKV13 144Mb; 667-1066 MHz 1.3 V; x18, x36 Burst 2 CY7C147/8xB 72Mb; 133-250 MHz 2.5, 3.3 V; x18, x36 CY7C144/6xA 36Mb; 133-250 MHz 2.5, 3.3 V; x36, x72 CY7C137/8xD 18Mb; 100-250 MHz 3.3 V; x18, x32, x36 CY7C135/6xC 9Mb; 100-250 MHz 3.3 V; x18, x32, x36 Auto E 7 CY7C134/2xG 2,4Mb; 100-250 MHz 3.3 V; x18, x32, x36 36Mb with ECC 2 133-250 MHz 2.5, 3.3 V; x18, x36 Contact Sales 18Mb with ECC 2 100-250 MHz 2.5, 3.3 V; x18, x36 Contact Sales CY7C161/2xKV18 144Mb; 250-333 MHz 1.8 V; x9, x18, x36 Burst 2, 4 CY7C141/2xKV18 36Mb; 250-333 MHz 1.8 V; x8, x9, x18, x36 Burst 2, 4 CY7C131/2/9xKV18 18Mb; 250-333 MHz 1.8 V; x8, x18, x36 Burst 2, 4 CY7C1911xKV18 18Mb; 250-333 MHz 1.8 V; x9 Burst 2, 4 CY7C151/2xKV18 72Mb; 250-333 MHz 1.8 V; x9, x18, x36 Burst 2, 4 CY7Cx4/5/6/7xKV18 144Mb; 300-550 MHz 1.8 V; x18, x36 Burst 2, 4 CY7Cx54/5/6/7KV18 72Mb; 250-550 MHz 1.8 V; x18, x36 RH 6 ; Burst 2, 4 CY7Cx24/5/6/7xKV18 36Mb; 400-550 MHz 1.8 V; x18, x36 Burst 2, 4 CY7Cx14/5/6/7xKV18 18Mb; 400-550 MHz 1.8 V; x18, x36 Burst 2, 4 CY7C156/7xXV18 72Mb; 366-633 MHz 1.8 V; x18, x36 Burst 2, 4 CY7C126/7x 36Mb; 366-633 MHz 1.8 V; x18, x36 Burst 2, 4 CY7C40xKV13 72Mb; 667-1066 MHz 1.3 V; x18, x36 Burst 2 72Mb with ECC 2 133-250 MHz 2.5, 3.3 V; x18, x36, x72 Contact Sales Random Transaction Rate NEW Roadmap

4. 001-96748 Owner: ABVYSynchronous SRAM With On-Chip ECC Quick Presentation Rev** Tech Lead: SKRG 4 Standard Sync SRAM With On-Chip ECC Switches and routers Radar and signal processing Test equipment Military and aerospace systems Applications Available in two modes: Flow-Through and Pipeline 2 Single-cycle (SCD) and double-cycle (DCD) 3 deselect options Bus-width configurations: x18, x36, x72 (72Mb) Two voltage options: 2.5 V and 3.3 V Industrial and commercial temperature grades Error-correcting code (ECC) to detect and correct single-bit errors Packages: 165 BGA and 100 TQFP Industry-standard, RoHS 4 -compliant packages Features Preliminary Datasheet: Contact SalesContact Sales Collateral Family Table Sampling: Q2 2015 (36Mb), Q3 2015 (18Mb), Q1 2016 (72Mb) Production:Q2 2015 (36Mb), Q4 2015 (18Mb), Q2 2016 (72Mb) Availability Block Diagram OptionDensityMPNRTRFIT/Mb 1 Standard Sync with On-Chip ECC Pipeline 18 36 72 Mb CY7C1370/2K CY7C1440/2K CY7C1470/2K 250MT/s<0.01 Standard Sync with On-Chip ECC Flow-Through 18 36 72 Mb CY7C1371/3K CY7C1441/3K CY7C1471/3K 133MT/s<0.01 Data Port x18, x36, x72 x19-x21 Chip Enable Byte Write Data Port and Control (2.5/3.3V) Address Bus Control Input Register Output Register (Pipeline) Control Logic SRAM Array JTAG Interface x2 Clock Output Enable ECC Encoder ECC Decoder 1 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data 2 Modes of synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline) 3 Modes of operation in Pipeline mode where the output driver is tri-stated after either a single cycle (SCD) or dual cycle (DCD) of issuing the deselect command 4 A European Union directive intended to eliminate the use of environmentally hazardous material in electronic components Product Overview Address Interface Test Engine

5. 001-96748 Owner: ABVYSynchronous SRAM With On-Chip ECC Quick Presentation Rev** Tech Lead: SKRG 5 NoBL ® SRAM With On-Chip ECC Switches and routers Radar and signal processing Test equipment Military and aerospace systems Applications Available in two modes: Flow-Through and Pipeline 2 No Bus Latency™ (NoBL 3 ) architecture for balanced read and write Bus-width configurations: x18, x36, x72 (72Mb) Two voltage options: 2.5 V and 3.3 V Industrial and commercial temperature grades Error-correcting code (ECC) to detect and correct single-bit errors Packages: 165 BGA and 100 TQFP Industry-standard, RoHS 4 -compliant packages Features Preliminary Datasheet: Contact SalesContact Sales Collateral Family Table Sampling: Q2 2015 (36Mb), Q3 2015 (18Mb), Q1 2016 (72Mb) Production:Q2 2015 (36Mb), Q4 2015 (18Mb), Q2 2016 (72Mb) Availability Block Diagram Address Bus Input Register Output Register (Pipeline) SRAM Array JTAG Interface Control x2 Clock Output Enable ECC Encoder ECC Decoder Address Interface Test Engine Data Port Chip Enable Byte Write OptionDensityMPNRTRFIT/Mb 1 NoBL ® with On-Chip ECC Pipeline 18 36 72 Mb CY7C1380/2K CY7C1460/2K CY7C1480/2K 250MT/s<0.01 NoBL ® with On-Chip ECC Flow-Through 18 36 72 Mb CY7C1381/3K CY7C1461/3K CY7C1481/3K 133MT/s<0.01 1 The projected failure rate of a device; one FIT/Mb equals one failure per billion device hours per megabit of data 2 Modes of synchronous SRAM operation that optimize either read latency (Flow-Through) or operating frequency (Pipeline) 3 A Synchronous SRAM that transfers data on the rising edge of the clock signal with zero clock cycle delay between read and write operations 4 A European Union directive intended to eliminate the use of environmentally hazardous material in electronic components x19-x21 x18, x36, x72 Product Overview NoBL Logic Data Port and Control (2.5/3.3V)

6. 001-96748 Owner: ABVYSynchronous SRAM With On-Chip ECC Quick Presentation Rev** Tech Lead: SKRG 6 1. Visit the Cypress Synchronous SRAM with ECC web page to learn moreweb page 2. Download the Synchronous SRAM Roadmap, which includes the Synchronous SRAM with ECC Product OverviewSynchronous SRAM Roadmap 3. Contact Sales to request a preliminary datasheetContact Sales Here’s How to Get Started Getting Started