1. A 0.6V 205MHz 19.5ns tRC 16Mb Embedded DRAM VLSI Systems I A 0.6V 205MHz 19.5ns tRC 16Mb Embedded DRAM K. Hardee, F. Jones, D. Butler, M. Parris, M. Mound, H. Calendar, G. Jones, L. Aldrich, C. Gruenschlaeger, M. Miyabayashi, K. Taniguchi, T. Arakawa

2. A 0.6V 205MHz 19.5ns tRC 16Mb Embedded DRAM VLSI Systems I Overview Primary use –Embedded DRAM Uniqueness claim –Ultra-low supply voltage (0.6V) for low power consumption Difficulties of low voltage operation –Reduced transistor thresholds cause greater off current –At low voltages, circuit speed is more dependent on manufacturing variations –Low voltages make bitline sensing more difficult

3. A 0.6V 205MHz 19.5ns tRC 16Mb Embedded DRAM VLSI Systems I Overview (continued) Solution #1 –Current through reference transistor is monitored and body bias is regulated to increase Vt during quiescent periods –Improves speed for slow process conditions by 63% –Reduces leakage current by 75% Solution #2 –A sleep mode is introduced that further reduces leakage current Solution #3 –Extra low Vt (0.2V) transistors are used to provide low-voltage sensing for bitlines

4. A 0.6V 205MHz 19.5ns tRC 16Mb Embedded DRAM VLSI Systems I Detailed Specifications Size16Mb Power Supply0.7V & 2.5V Cell Size0.195um 2 Cell Capacitance40fF Bitline BiasVcc/2 =.35V Maximum Refresh Time128ms Maximum Cells / Row128 Interface / ClockingSDR External IO Voltage3.0V Number of Banks4