1. Computer Organization CSC 405 (VSC) Very Simple Computer

2. Very Simple Computer (VSC) For detailed design information on the VSC, please read the Very Simple Computer Overview. The VSC is a very impractical computer system with a single Bus, a 32 8-bit Word memory, switch/LED input/output, supporting 8 instructions. As simple as it is, the VSC is a complete representation of the Von Neumann Architecture. Registers: PC - program counter IR - instruction register MAR - memory address register LAT1 - latch 1, ALU input register LAT2 - latch 2, ALU input register ACC - accumulator, ALU output register VSC Functional Units: I/O - input output unit CU - control unit MU - memory unit ALU - arithmetic/logic unit

3. A Walk through the Fetch/Execute Cycle MAR <- PC IR <- MEM[MAR] PC <- PC+1 MAR <- IR 0-4 LAT1 <- MEM[MAR] LAT2 <- ACC EXE en

4. The Instructions of the VSC The eight instructions of the VSC are based on the Post/Turing language. These instructions form a complete set of operations. While not very practical, the operations of the Post/Turing language can be used to emulate any computable function. LDA - load the accumulator with a word from memory (selected by MAR) STA - store the word in the accumulator into memory (at address in MAR) ADD - add LAT1 and LAT2 and store the result into the accumulator (ACC) CMP - complement (bit inverse) the value in LAT1 and store in accumulator BNN - if the MSB of ACC is zero (0) replace PC with address in IR SHL - perform an arithmetic shift left on the value in LAT1 SHR - perform an arithmetic shift right on the value in LAT1 HLT - stop the fetch/execute cycle (for VSC set PC to 11111)

5. Register Transfers for Instruction Executions 000 LDA ACC <- MEM[MAR] 001 STA MEM[MAR] <- ACC 010 ADD ACC <- LAT1+LAT2 011 CMP ACC <- LAT1 100 BNN IF ACC 7 =0 THEN PC <- IR 0-4 101 SHL ACC <- 2*LAT1 110 SHR ACC <- LAT1/2 111 HLT PC <- 11111 OpCode ASM Register Transfer There is a different register transfer operation for each of the eight instructions of the VSC. The Control Unit is a combinatorial circuit (encoder) that activates the read and write enable lines that correspond to the operation indicated by the OpCode.

6. Implementing the Register Transfers in Hardware We have defined the registers for the VSC, the functional blocks (units) and the logic for the fetch/execute cycle. Now we need to design the circuitry that will invoke these register transfers. There are 7 steps in the fetch/execute cycle. We will use a divide-by-eight counter to generate the Read and Write enable signals for each step. 000 100 110 010 111001 101011 start 1 MAR <- PC 2 IR <- MEM[MAR] 3 PC <- PC+1 4 MAR <- IR 0-4 5 LAT1<- MEM[MAR] 6 LAT2<- ACC 7 EXE en 8 No Op Time 0 1 2 3 4 5 6 7 MAR RE PC RE PC WE PC INC IR RE IR WE LAT1 RE LAT2 RE MEM RE MEM WE ACC RE ACC WE EXE EN

7. 555 Timer Divide by 8 Counter 3-to-8 Decoder 0123456701234567 MAR RE PC RE PC WE PC INC IR RE IR WE LAT1 RE LAT2 RE MEM RE MEM WE ACC RE ACC WE EXE EN The clock pulses that drive the divide-by-eight counter can be produced with a timer circuit (built from a  A555). The divide-by-eight counter is available in a single TTL IC (7493). The 3-to-8 decoder can be built by inverting the outputs of a popular decoder IC (74138).

8. A similar circuit can be built to generate the control signals needed to implement each of the eight instructions of the VSC. In this case, the control lines input to the 3-to-8 decoder come directly from the OpCode of the current instruction in IR 5-7. 000 LDA ACC <- MEM[MAR] 001 STA MEM[MAR] <- ACC 010 ADD ACC <- LAT1+LAT2 011 CMP ACC <- LAT1 100 BNN if ACC 7 =0 then PC<-IR 0-4 101 SHL ACC <- 2*LAT1 110 SHR ACC <- LAT1/2 111 HLT PC <- 11111 OpCode ASM Register Transfer Note: Enable lines in common with those in the fetch circuit must be connected through OR gates. MEM RE 3-to-8 Decoder IR OpCode 7 6 5 4 3 2 1 0 ACC RE ACC WE MEM RE MEM WE PC RE IR WE ADD EN CMP EN SHL EN SHR EN HLT ACC 7

9. We can define an assembler to write programs for the VSC. This assembler will be used to help us manually develop machine code (1’s and 0’s) for the VSC. The best way to become familiar with the VSC assembler is by reviewing a few examples: In our first example we will write a program to add the values 6 and 3. We will preload these values into memory labeled X and Y and have the program store the result in Z. VSC ASM Addr Data/Instr LDA X 00000 00000100 ADD Y 00001 01000101 STA Z 00010 00100110 HLT 00011 11111111 X 6 00100 00000110 Y 3 00101 00000011 Z 0 00110 00000000 Note that the assembly language commands are simply the 8 operations we defined for the VSC and their corresponding op-codes are the 3 highest-order bits of each instruction. The program is placed in memory with the 1st instruction at address 0000. Upon completion the VSC should hold the value 00001001 at memory address 00110.

10. The next example is a program that checks an input value X. If X is even then it is divided by 2 otherwise it is multiplied by 2. The result replaces X. In this example X=7. LDA X0000000010001 SHR0000111000000 SHL00010 10100000 STA Y0001100110010 LDA X 0010000010001 CMP0010101100000 ADD ONE 0011001010011 ADD Y 0011101010010 BNN EVEN0100010001101 LDA X 0100100001111 ODD SHL 0101010100000 LDA ZERO 0101100010100 BNN SAVE 0110010001111 EVEN LDA X 0110100010001 SHR 0111011000000 SAVE STA X 0111100110001 HLT 1000011111111 X [INPUT] 1000100000111 Y 0 1001000000000 ONE 1 1001100000001 ZERO 0 1010000000000 First the value of X is loaded into the accumulator. Then it is divided and multiplied by 2. The value of X is subtracted from this result (Y). If the difference is negative then X was odd so X is loaded and multiplied by 2. The program then jumps to the address labeled SAVE. If the difference is zero (i.e. not negative) then X was even so X is loaded and divided by 2. The program then saves the result back into X. Homework: Write a VSC assember program that computes the sum of the first 10 integers. Use the pseuodo-code as shown in the last two examples.