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Senior Design 1 University of Portland School of Engineering.

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Presentation on theme: "Senior Design 1 University of Portland School of Engineering."— Presentation transcript:

1 Senior Design 1 University of Portland School of Engineering

2 Project LED Cube Team Stolen Pie –Patrick Bloem –Jess Tate –Devin Pentecost –Caleb Pentecost University of Portland School of Engineering Advisor Dr. Osterberg Industry Representative TBD

3 Senior Design 3 Introduction An Interactive 3D MEMS Display Uses accelerometers LED Cube (Animation) University of Portland School of Engineering

4 Senior Design 4 University of Portland School of Engineering Project Proposal Functional Specification MOSIS Chip Design and Macro Model Creation MOSIS Fabrication (by foundry) Design Document Construct Cube Assemble Circuits Test and Debug Founder's Day Display Software Frameworking Microcontroller Programming Design Approach

5 Senior Design 5 University of Portland School of Engineering Top Level System Diagram

6 Senior Design 6 Top Level Schematic University of Portland School of Engineering

7 Senior Design 7 University of Portland School of Engineering Milestones StatusDescription Original Target Previous Target Present Target CompleteTop Level MOSIS block diagram complete10/16/11 CompleteTop level microcontroller design complete10/23/11 CompleteInitial B2Logic Edif Files Complete10/31/11 CompleteCube mock-up and pinout complete11/6/11 CompleteDesign Document v0.911/12/11 CompleteFinal Budget Complete11/12/11 CompleteDesign Document v1.0 approved11/19/11 CompleteFinal MOSIS Edif Files complete11/21/11 On TrackInitial CPLD/FPGA Macro Model Complete12/4/11 12/9/11 On TrackPeer Evaluations/Lab Notebooks Due12/5/11 On Track Place casing request1/27/12 On Track CPLDs programmed and determined if functional 2/3/12 On Track Wire wrap tutorial complete2/10/12 On Track LED cube constructed2/24/12 On Track Circuit complete with macro models3/9/12

8 Senior Design 8 Accomplishments Final Budget Complete Design Document v1.0 approved Final MOSIS Edif Files complete 555 Timer Experiment Accelerometer Experiment University of Portland School of Engineering

9 Senior Design 9 Accomplishment: Final MOSIS complete University of Portland School of Engineering

10 Senior Design 10 Accomplishment: Final MOSIS complete University of Portland School of Engineering

11 Senior Design 11 Accomplishment: 555 Timer Experiment University of Portland School of Engineering

12 Senior Design 12 Accomplishment: 555 Timer Experiment Results University of Portland School of Engineering Well above 60 frames/second!

13 Senior Design 13 Accomplishment: Accelerometer Experiment University of Portland School of Engineering Demonstration

14 Senior Design 14 Plans Complete Initial CPLD/FPGA Macro Model Complete Peer Evaluations University of Portland School of Engineering

15 Senior Design 15 Concerns/Issues Box Construction Techniques –Debugging/Access FPGA/CPLD Confirmation –No experiments have been done with these devices yet. University of Portland School of Engineering

16 Senior Design 16 Conclusions Project is on schedule. Design going well. University of Portland School of Engineering


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