1. M. Bruschi – INFN Bologna (ITALY) 1 Electronics, Trigger and DAQ General Architecture of the system for phase I Parts of the system which are already available/tested or in advanced design phase What is needed for phase I The possible temporary solution for 2007 The calibration system Conclusions

2. M. Bruschi – INFN Bologna (ITALY) 2 General Architecture of the system for phase I

3. M. Bruschi – INFN Bologna (ITALY) 3 LUCID Readout Goals The basic operation of the LUCID electronics is to count the track multiplicity per bunch crossing in the detector The track multiplicity in a Cerenkov tube is proportional to the light signal collected by a photosensitive device (in our case PMT or MAPMT) In the baseline readout scheme proposed for phase I the light produced in a single Cerenkov tube will be readout directly by a single PMT device and the amplitude and time of arrival of the signal will be used to count the detector track multiplicity. In the second readout scheme the light produced in a single tube will be split in many (up to 16) groups of quartz fibers connected to a MAPMT placed in a moderately low radiation area (5 Gy/year at highest lumi). The LUCID information relevant to measure the luminosity of the experiment must be available: 1.in the global ATLAS triggered event 2.in the online monitor 3.to possibly form a trigger for interaction or high event multiplicity rejection.

4. M. Bruschi – INFN Bologna (ITALY) 4 Readout Schemes for Phase I LUCIDNose Sh. USA15 ~4m ~80-100 m Number of channels (per detector side): 16 PMT/ 1 MAPMT (4 ch.) The front end has been conceived as having as least components as possible for two reasons: - short time to produce it (from April 2006) - it is deployed in an area that during is not easily accessible LUCID +PMT PMT FED ROD TRIGGER LUCID MAMPT FED (MAROC) coaxial Shielded Tw. Pair Quartz Fibers ROD TRIGGER Shielded Tw. Pair/optical fibers 1) 2)

5. M. Bruschi – INFN Bologna (ITALY) 5 Baseline Readout Scheme Description Signals from PMT are fed into a PMT FED card (formed by a PMT mother card and PMT daughters cards both tested on Dec. 06) providing the necessary amplification. The differential output is sent to USA15 via twisted pair shielded cable The received analog signal is processed by a ROD CARD. The multiplicity per tube is evaluated by LUT combining time of arrival and amplitude information. The result of the processing is stored in pipeline to be read pending a L1A and sent directly to the trigger card The TRIGGER CARD processes the multiplicity from all the tubes and forms the LUCID trigger (interaction/high multiplicity rejection/ …). Online luminosity scalers are implemented in the logic and readout via VME. The processed data, stored in a pipeline, are sent to ROS pending a L1A and form part of the LUCID event. The design of the TRIGGER CARD is already started since it must be used also in another project expected to run this year (R&D on a fast tracking trigger for silicon devices) In case the ROD CARD were not available for the end of this year we propose a temporary readout solution for 2007 based on the TRIGGER CARD plus a VME based system. The online luminosity and trigger features would still be available while the system debugging would be performed via the VME QDC system (tested on Dec. 06) The feature of time arrival of the event readout will be in this case added to the system tested on Dec. 06 by means of a Constant Fraction Discriminator (CFD) card already in the production phase and of a VME TDC module

6. M. Bruschi – INFN Bologna (ITALY) 6 LUCID READOUT+TRIGGER (PHASE I) PMT 1 RODROD PMT 16 MAMPT FED (MAROC) 4 diff. TX lines GOL LINK+TTCRQ TRIGGERCARDTRIGGERCARD RODROD 100 m FED USA 15 HV, LV, SLOW CONTROL ROS TTCRQ To LVL1 VME IF OnLine LUMI PMT FED

7. M. Bruschi – INFN Bologna (ITALY) 7 The FED CARDS PMF: HV Divider Signal Routing MAROC chip MAPMT FED PMT MOTHER CARD 1 2 3 16 PMT DAUGHTER CARDS InOut PMT FED Amplifier+ Diff. Line Drivers MAROC (ROMAN POTS): 4 SUM OVER 16 CHANNELS (ANALOG OUT) 64 THR. DISCRIMINATOR (DIGITAL OUT/GOL LINKS) MRO

8. M. Bruschi – INFN Bologna (ITALY) 8 stru 1 stru 2 stru 16 GOL RX LVDS S/P 3 3 3 LVDS 1 (to trig. unit) LVDS 2 (to trig. unit) LVDS 3 (to trig. unit) LVDS 4 (to trig. unit) stru 2 TTCRQ i.f. opt. lnk from TTCEX VME P1 VME I.F DPRAM CTRL LOGIC 6 Bytes EVENT BUFFER s-LINK to ROS from CTRL LOGIC 160 MB/s s-LINK Busy LUCID ROD CARD (2+2units ) – VME 9U Analog_In 1 Analog_In 2 Analog_In 16 GOL_In 1 GOL_In 2 GOL_In 10 ~200 Bytes/ev

9. M. Bruschi – INFN Bologna (ITALY) 9 Single Tube Readout Unit 20 ns int 5 ns reset 25 ns time LHC Clock LHC Int. Time ADC GATE to the trigger unit Fan Out GI + ADC Multiplicity per Tube LUT 8 1 3 TUBE LUT (1 MB) 3 #1 #16 GOL LINK 1/4 data from the MRO DIFF. ANALOG INPUT (FROM FED) STRU CFD (Prog. Thr +NR) ADC GATE RAW DATA TO READOUT per STRU  ~ 6 Bytes/BC 1 2 20 Progr. GATE & DEL LHC Clock Note: the dashed components are used only for the MAPMT readout scheme

10. M. Bruschi – INFN Bologna (ITALY) 10 Signal Buffer TTCRQ i.f. opt. lnk from TTCEX VME P1 VME I.F CTRL LOGIC s-LINK to ROS 160 MB/s s-LINK Busy LUCID TRIGGER CARD (1 unit ) – VME 9U Detector1Detector1 Detector2Detector2 LVDS 1 LVDS 2 Signal Buffer FPGA based TRIGGER PROCESSING UNIT 5 ser. Inp 60 bit/BC 5 ser. Inp 60 bit/BC to the L1 trigger ~40 Bytes/ev FPGA: Algorithm Flexibility LVDS 3 LVDS 4 LVDS 5 LVDS 1 LVDS 2 LVDS 3 LVDS 4 LVDS 5 ONLINE LUMINOSITY SCALERS

11. M. Bruschi – INFN Bologna (ITALY) 11 Scalers in the Trigger Card (Firmware) for Online Luminosity LUCID ALUCID C II. Particle Counting I. Collision/Zero Counting 16 tubes 1 2 3 4  4 x 3564 x 32bit ~ 60kB (1-4 x BCIDs x Scaler depth) 1 2 (If LUCID A-C Coincidence) 3 4 (If LUCID A-C Coincidence)  4 x 3564 x 32bit ~ 60kB III. Total Orbit Counter For normalization (Average) All scalers start/stop are synchronized with the Orbit signal to scale over the same interval at a BC precision Scalers are incremented on L1A (for dead time correction) Scalers read-out by VME and sent to DCS (~ 120 kB for each Luminosity Block –few min-) for processing, to be published at any time  32bit

12. M. Bruschi – INFN Bologna (ITALY) 12 The LUCID Data Flow LUCID Run Control Luminosity Block DCS IS CTP/LVL1 Dead-time Pre-scale LVL2 + EF Pre-scale ATLAS TDAQ Offline Luminosity Luminosity data stream Control Room Conditions Database Analysis LUCID Trigger (X Hz) L1A ~100 kHz (~1 kHz) ~200 Hz (~2 Hz) ROS… S-link Online Lum. Scalers (Ethernet) Cross checks with CTP Monitoring SBC (VME) LB (Ethernet)

13. M. Bruschi – INFN Bologna (ITALY) 13 Parts of the system which are already available/tested or in advanced design phase

14. M. Bruschi – INFN Bologna (ITALY) 14 The prototype PMT FED Test Board MAPMT PMT Inputs MAPMT HV ANALOG SIGNAL Outputs (18x4) x10 x5 2ch Preamp+Driver PMT Daughter Card Mother Card

15. M. Bruschi – INFN Bologna (ITALY) 15 The prototype TX-RX System TX system: PMT Mother Card + 36 Daughter Cards x2÷4 PZ adj Gain adj DEC. 06 Test DAQ 7 VME RX cards SBC CORBO QDC ADC SCALER ATLAS TDAQ-01-06-01 RX system: VME RX card 8 channels PZ adj Gain adj

16. M. Bruschi – INFN Bologna (ITALY) 16 Signal Characteristics PMT: R2496 Cable length=100 m Source: Led pulses The pole-zero correction performed by the RX card to compensate for cable losses works properly Cable length=100 m Source: Pulser

17. M. Bruschi – INFN Bologna (ITALY) 17 The Electronics Gain Measured at the Dec. 06 Test Beam PMT 2 QDC CH 2 PMT 2 TXRX QDC CH 2 100 m cable S= 28.7 N=0.56 S= 345.2 N=6.7 GAIN=345.2/28.7~12 (S/N)=51.4 to be compared with 51.3 No S/N worsening observed Good linearity and uniformity of response

18. M. Bruschi – INFN Bologna (ITALY) 18 TDAQ-01-06-01 at the DEC. 06 Test Beam During the December 2006 Test Beam we took data using the last version of TDAQ and the following VME modules: 1 SBC + Hard Drive (Standalone mode) 1 CORBO (Trigger and Busy) 2 CAEN QDC V792 1 CAEN SCALER 1 CAEN SEQUENCER V551 2 CAEN ADC V550

19. M. Bruschi – INFN Bologna (ITALY) 19 The CFD card We are producing (the design is completed) a Constant Fraction Discriminator card which will be used: 1.to test the timing performances of the readout chain 2.as system block for the possible temporary solution in 2007 (see next) Each VME 6U card will handle 8 channels CFD ANALOG (TO QDC) FROM VME RX CARD OUTPUT LVDS (TO TDC) LVDS (TO TRIGGER CARD) NIM (AUXILIARY)

20. M. Bruschi – INFN Bologna (ITALY) 20 THE TRIGGER CARD (SLIM/LUCID) We merged the need of two projects (SLIM/LUCID) in a unique Trigger Card (EDRO) whose design is already started The specific purpose of each project will be defined by the design of the Mezzanine (input signals routing) and of the FPGAs firmware ALTERA STRATIX II EP2S130F1508

21. M. Bruschi – INFN Bologna (ITALY) 21 What is Needed for phase I ITEMSTATUSAVAILABLE PMT FED: PMT mother card TO BE MODIFIEDSpring ‘07 MAPMT FED: PMF TO BE MODIFIEDSpring ‘07 MAPMT FED: MRO DBT,DBR,DBF (PRODUCTION) ANB,DBB * (TO BE DESIGNED) Spring ‘07 CFD cardPRODUCTIONSpring ‘07 TRIGGER cardDESIGN STARTEDFall ‘07 ROD cardTO BE DESIGNED2007/8 * NOT DIFFICULT DESIGN. MOSTLY SIGNAL ROUTING MRO

22. M. Bruschi – INFN Bologna (ITALY) 22 The possible temporary solution for 2007 (in case ROD card not available) PMT 1 PMT 16 MAMPT FED MAROC 4 diff. TX lines TRIGGERCARDTRIGGERCARD 100 m FED USA 15 HV, LV, SLOW CONTROL ROS TTCRQ To LVL1 VME IF OnLine LUMI 3 RX B O A R D S 3 CF D B O A R D S 20 VME QDC/TDC INTEGRATED ON TDAQ ONLINE SCALERS DEBUGGING VIA VME MAROC DIGITAL PART NOT AVAILABLE

23. M. Bruschi – INFN Bologna (ITALY) 23 LED Calibration System - I The readout chain gain will be measured using a calibration system based on LED light. We tested already such a system during the past test beam  The small amount of channels to be tested will allow to use the simple manual method used during the test beam An improved version (VME programmable system, fully automatic ) is under design

24. M. Bruschi – INFN Bologna (ITALY) 24 LED Calibration System - II PULSER Amplitude: ~ 4 V (variable in 10 mV steps) Duration: ~ 20 ns Trigger Output (to the DAQ trigger logic) Led amplitude adjusted to see the single photoelectron signal LED CARD PMT Optical Fiber LUCID TUBE

25. M. Bruschi – INFN Bologna (ITALY) 25 Conclusions An intense work for design and debugging the electronics solutions for LUCID has been performed during the last year Tests on important elements for the FED and DAQ system of phase I have been successfully performed during the last test beam on December We are reasonably confident that the phase I detector can be run integrated in the ATLAS TDAQ starting from the end of this year providing valuable and unique information for the experiment online and offline luminosity determination

26. M. Bruschi – INFN Bologna (ITALY) 26 Backup Slides

27. M. Bruschi – INFN Bologna (ITALY) 27 Description of some of the building blocks of the readout electronics OPERA MAROC CHIP Adapted to LUCID needs from the RP design (ATLAS Orsay group) Gated Integrator + ADC 8 bit for the total sum should be enough Contacts have been taken with the LHCb preshower group (Clermont) for adapting their GI+ADC solution LOGIC Mainly Based on LUT IMPLEMENTED on FPGAs Flexible and robust ENGINEERING Integration in standard VME 9U

28. M. Bruschi – INFN Bologna (ITALY) 28 Fibers readout scheme description The high radiation dose level around LUCID in phase II suggests the possibility to transmit the light collected by the Cerenkov tubes on rad. hard quartz fibers (typ. ~60 fibers/tube grouped in up to 16 readout channel) to the front end electronics sitting on a low level irradiated area (nose shielding, 5 Gy/year) Charged tracks crossing the fibers at an angle off the fiber axis could produce unwanted light (background) The signals affected by this kind of background can be rejected by examining the pattern of hit fibers (and not only the total amount of light collected by the fibers) The front end chip developed by the ROMAN POT group (MAROC) to read MAPMT (8x8 matrix of readout channel) offers the possibility to produce, for each tube: 1.An analog signal proportional to the light produced in the cerenkov tube (this feature was added for LUCID) 2.A digital signal based on the fast discrimination of the single MAPMT readout channel (used to study the pattern of hit fibers) No event Signal event Background event

29. M. Bruschi – INFN Bologna (ITALY) 29 The MAROC CHIP LUCID ANALOG LUCID DIGITAL LUCID SLOW CTRL The MAROC chip design (ROMAN POT) has been modified in order to group up to 16 channel (ANALOG SUM)

30. M. Bruschi – INFN Bologna (ITALY) 30 LUCID FED (for MAPMT)

31. M. Bruschi – INFN Bologna (ITALY) 31 LUCID FED (for MAPMT) The FED will sit in an area irradiated by 5 Gy/year at max. luminosity Nevertheless, also for phase I, all radiation tolerant components have been used (GOL, TTCrq, ELMB, voltage regulators LHC4913, FPGA Flash ACTEL APA and CPLD Xilinx XC9500) In the FPGAs, the Triple Module Redundancy logic has been implemented All the cards are in production except the analog one (BUT: the basic analog circuit is already produced and tested) Prototype (with MAROC2) ready in spring

32. M. Bruschi – INFN Bologna (ITALY) 32 AVERAGE ANODE CURRENT DRAWN BY PMT IN PHASE I Total average current per tube: 8  A

33. M. Bruschi – INFN Bologna (ITALY) 33 AVERAGE ANODE CURRENT DRAWN BY MAPMT IN PHASE I 10 fiber/tube (40 channel/MAPMT) Total average current per tube: 1.6  A