1. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 1 Raimund Ubar Tallinn Technical University D&T Laboratory Estonia Hierarchical Defect-Oriented Test Generation REASON Tutorial Sofia, May 29, 2004

2. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 2 Abstract How to improve the testing quality at increasing complexities of today's systems? Two main trends: defect-oriented test and high-level modelling –Both are caused by the increasing complexities of systems based on deep- submicron technologies The complexity problems in testing digital systems are handled by raising the abstraction levels from gate to register-transfer level (RTL) instruction set architecture (ISA) or behavioral levels To handle defects in circuits implemented in deep-submicron technologies, new fault models and defect-oriented test methods should be used Trends to high-level modelling and defect-orientation are opposite As a promising compromise and solution is: to combine hierarchical approach with defect orientation Decision Diagrams serve as a good tool for hierarchical modelling of defects in digital systems

3. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 3 Outline Introduction to Digital Test (3) How to improve test quality at increasing complexity of systems (11) High-level modelling and defect-orientation (6) Decision Diagrams - beyond BDDs (8) Hierarchical test generation (11) –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Conclusions

4. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 4 Introduction: the Problem is Money? Cost of testing Quality Cost of quality Cost Cost of the fault 100% 0% Optimum test / quality How to succeed? Try too hard! How to fail? Try too hard! (From American Wisdom) Conclusion: “The problem of testing can only be contained not solved” T.Williams Test coverage function Time 100%

5. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 5 Introduction: How Much to Test? Paradox: 2 64 input patterns (!) for 32-bit accumulator will be not enough. A short will change the circuit into sequential one, and you will need because of that 2 65 input patterns Paradox: Mathematicians counted that Intel 8080 needed for exhaustive testing 37 (!) years Manufacturer did it by 10 seconds Majority of functions will never activated during the lifetime of the system Time can be your best friend or your worst enemy (Ray Charles) & & x1x1 x2x2 x3x3 y State q Y = F(x 1, x 2, x 3,q) * 1 1 Y = F(x 1, x 2, x 3 ) Bridging fault 0

6. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 6 Introduction: Hierarchy Paradox: To generate a test for a block in a system, the computer needed 2 days and 2 nights An engineer did it by hand with 15 minutes So, why computers? The best place to start is with a good title. Then build a song around it. (Wisdom of country music) System 16 bit counter & 1 Sequence of 2 16 bits Sea of gates

7. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 7 Two Approaches to Testing Testing of functions: 0% Faulty functions covered by 1. pattern Faulty functions covered by 2. pattern 50% 75% 3. pattern 4. pat. 87,5% 93,75% 1 2 n Combinational circuit under test Truth table Patterns 00…000 00…001 00…010 … 11…111 Functions 01 01 01…101 00 11 00…011 00 00 11…111 … 00 00 00…111 2n2n2n2n 1 1 2n2n2n2n 2 Number of patterns Number of functions 2 n 2 n-1 2 tested 50%!

8. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 8 Two Approaches to Testing Testing of structural faults: 1 2 n Combinational circuit under test Faults covered by 1. pattern 2. pattern 3. pat. 4. pat. Not tested faults Fault coverage 100% Number of patterns 4

9. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 9 Two Approaches to Testing Testing of functions: 0% Faulty functions covered by 1. pattern Faulty functions covered by 2. pattern 100% will be reached only after 2 n test patterns 75% 3. pattern 4. pat. 87,5% 93,75% Testing of structural faults: Faults covered by 1. pattern 2. pattern 3. pat. 4. pat. Not tested faults 100% will be reached when all faults from the fault list are covered

10. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 10 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation Decision Diagrams (beyond BDDs) Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Conclusions

11. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 11 Complexity vs. Quality Problems: Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importance because of the complexity reasons Traditional Stuck-at Fault (SAF) model does not quarantee the quality for deep-submicron technologies New solutions: The complexity can be reduced by raising the abstraction levels from gate to RTL, ISA, and behavioral levels –But this moves us even more away from the real life of defects (!) To handle adequately defects in deep-submicron technologies, new fault models and defect-oriented test generation methods should be used –But, this is increasing even more the complexity (!) To get out from the deadlock, these two opposite trends should be combined into hierarchical approaches

12. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 12 Fault and defect modeling Defects, errors and faults An instance of an incorrect operation of the system being tested is referred to as an error The causes of the observed errors may be design errors or physical faults - defects Physical faults do not allow a direct mathematical treatment of testing and diagnosis The solution is to deal with fault models System Component Defect Error Fault

13. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 13 Transistor Level Faults Stuck-at-1 Broken (change of the function) Bridging Stuck-open  New State Stuck-on (change of the function) Short (change of the function) Stuck-off (change of the function) Stuck-at-0 SAF-model is not able to cover all the transistor level defects How to model transistor defects ?

14. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 14 Mapping Transistor Faults to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Generic function with defect: Function: Faulty function: A transistor fault causes a change in a logic function not representable by SAF model Defect variable: d =d = 0 – defect d is missing 1 – defect d is present Mapping the physical defect onto the logic level by solving the equation:

15. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 15 Mapping Transistor Faults to Logic Level Short x1x1 x2x2 x3x3 x4x4 x5x5 y Test calculation by Boolean derivative: Generic function with defect: Function: Faulty function:

16. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 16 Functional Fault vs. Stuck-at Fault No Full SAF-TestTest for the defect x1x1 x2x2 x3x3 x4x4 x5x5 x1x1 x2x2 x3x3 x4x4 x5x5 1 1110-10-01 2 0--111-001 3 0110101110 4 10110 5 110-0 Full 100% Stuck-at-Fault-Test is not able to detect the short: The full SAF test is not covering any of the patterns able to detect the given transistor defect  Functional fault

17. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 17 Generalization: Functional Fault Model Constraints calculation: y Component F(x 1,x 2,…,x n ) Defect WdWd Component with defect: Logical constraints Fault-free Faulty Fault model: (dy,W d ), (dy,{W k d }) Constraints: d = 1, if the defect is present

18. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 18 Fault Table: Mapping Defects to Faults

19. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 19 Functional Fault Model for Stuck-ON Stuck-on x1x1 x2x2 Y V DD V SS x1x1 x2x2 NOR gate Conducting path for “10” RNRN RPRP x1x1 x2x2 yydyd 0011 0100 100Z: V Y 1100 Condition of the fault potential detecting:

20. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 20 Functional Fault Model for Stuck-Open Stuck-off (open) x1x1 x2x2 Y V DD V SS x2x2 NOR gate No conducting path from V DD to V SS for “10” x1x1 Test sequence is needed: 00,10 x1x1 x2x2 yydyd 0011 0100 100Y’ 1100 t x 1 x 2 y 1 0 0 1 2 1 0 1

21. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 21 Functional Fault Model Example: Bridging fault between leads x k and x l The condition means that in order to detect the short between leads x k and x l on the lead x k we have to assign to x k the value 1 and to x l the value 0. xkxk xlxl x* k d Wired-AND model x k *= f(x k,x l,d)

22. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 22 Functional Fault Model Example: x1x1 x2x2 x3x3 y & & x1x1 x2x2 x3x3 y & & & Equivalent faulty circuit: Bridging fault causes a feedback loop: Sequential constraints: A short between leads x k and x l changes the combinational circuit into sequential one t x 1 x 2 x 3 y 1 0 2 1 1 1 1

23. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 23 First Step to Quality How to improve the test quality at the increasing complexity of systems? First step to solution: Functional fault model was introduced as a means for mapping physical defects from the transistor or layout level to the logic level System Component Low level k WFkWFk WSkWSk Surrounding Bridging fault Mapping High level

24. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 24 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect- orientation Decision Diagrams (beyond BDDs) Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Conclusions

25. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 25 Register Level Fault Models K: ( If T,C) R D  F(R S1, R S2, … R Sm ),  N RTL statement: K- label T- timing condition C- logical condition R D - destination register R S - source register F- operation (microoperation)  - data transfer  N- jump to the next statement Components (variables) of the statement: RT level faults: K  K’- label faults T  T’- timing faults C  C’- logical condition faults R D  R D - register decoding faults R S  R S - data storage faults F  F’- operation decoding faults  - data transfer faults  N - control faults (F)  (F)’ - data manipulation faults

26. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 26 Fault Models for High-Level Components Decoder: - instead of correct line, incorrect is activated - in addition to correct line, additional line is activated - no lines are activated Multiplexer ( n inputs log 2 n control lines): - stuck-at - 0 (1) on inputs - another input (instead of, additional) - value, followed by its complement - value, followed by its complement on a line whose address differs in 1 bit Memory fault models: - one or more cells stuck-at - 0 (1) - two or more cells coupled

27. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 27 Fault models and Tests Dedicated functional fault model for multiplexer: –stuck-at-0 (1) on inputs, –another input (instead of, additional) –value, followed by its complement –value, followed by its complement on a line whose address differs in one bit Functional fault model Test description

28. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 28 Faults and Test Generation Hierarchy Circuit Module System Network of gates Gat e Functional approach F ki Test F k W F ki W S F Test W F k W S k Structural approach Network of modules W d ki Interpretation of W F k : - as a test on the lower level - as a functional fault on the higher level Higher Level Module Component Lower level kiki W F ki W S ki Surrounding Bridging fault k WFkWFk

29. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 29 Hierarchical Defect-Oriented Test Analysis BDDs DDs

30. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 30 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation Decision Diagrams (beyond BDDs) Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Conclusions

31. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 31 Binary Decision Diagrams x1x1 x2x2 y x3x3 x4x4 x5x5 x6x6 x7x7 0 1 Simulation: 0 1 1 0 1 0 0 Boolean derivative: 1 0 Functional BDD

32. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 32 Elementary Binary Decision Diagrams Elementary BDDs: 1 x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 & x2x2 x3x3 y x1x1 x1x1 x2x2 x3x3 1 x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 + x1x1 x2x2 x3x3 y x1x1 x2x2 x3x3 yx2x2 x3x3 Adder NOR AND OR

33. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 33 Building a SSBDD for a Circuit & 1 1 x1x1 x2x2 x3x3 x 21 x 22 y a b a b y a x1x1 x 21 b x 22 x3x3 a y x3x3 y x3x3 x1x1 x 21 DD-library: Superposition of DDs  Superposition of Boolean functions: Given circuit: Compare to SSBDD Structurally Synthesized BDDs: ba

34. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 34 Representing by SSBDD a Circuit & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro 6 7373 1 2 5 7272 7171 y 0 1 y = c y e y = c y  e y = x 6,e,y x 73,e,y  d ey b ey y = x 6 x 73  ( x 1  x 2 x 71 ) ( x 5  x 72 ) Structurally synthesized BDD for a subcircuit (macro) To each node of the SSBDD a signal path in the circuit corresponds

35. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 35 Fault modeling on SSBDDs The nodes represent signal paths through gates Two possible faults of a DD-node represent all the stuck-at faults along the signal path & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro 6 7373 1 2 5 7272 7171 y 0 1 Test pattern: 1 2 3 4 5 6 7 y 1 1 0 0 1 1

36. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 36 High-Level Decision Diagrams y 4 y 3 y 1 R 1 + R 2 IN + R 2 R 1 * R 2 IN* R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Superposition of High-Level DDs: A single DD for a subcircuit R2R2 R 2 + M 3 Instead of simulating all the components in the circuit, only a single path in the DD should be traced M1M1 M2M2

37. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 37 Fault Modeling on High Level DDs High-level DDs (RT-level): Terminal nodes represent: RTL-statement faults: data storage, data transfer, data manipulation faults Nonterminal nodes represent: RTL-statement faults: label, timing condition, logical condition, register decoding, operation decoding, control faults

38. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 38 Two trends: high-level modeling –to cope with complexity low-level modeling –to cope with physical defects, to reach higher acuracy Hierarchical Diagnostic Modeling Boolean differential algebra BDD-s High-Level DD-s

39. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 39 Outline Introduction to Digital Test How to improve test quality at increasing complexity of systems High-level modelling and defect-orientation Decision Diagrams (beyond BDDs) Hierarchical test generation –General concepts –Test generation for RT Level systems –Test generation for Microprocessors Conclusions

40. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 40 Hierarchical Test Generation In high-level symbolic test generation the test properties of components are often described in form of fault-propagation modes These modes will usually contain: –a list of control signals such that the data on input lines is reproduced without logic transformation at the output lines - I-path, or –a list of control signals that provide one-to-one mapping between data inputs and data outputs - F-path The I-paths and F-paths constitute connections for propagating test vectors from input ports (or any controllable points) to the inputs of the Module Under Test (MUT) and to propagate the test response to an output port (or any observable points) In the hierarchical approach, top-down and bottom-up strategies can be distinguished

41. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 41 Hierarchical Test Generation Approaches Bottom-up approach: Pre-calculated tests for components generated on low-level will be assembled at a higher level It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing However, the bottom-up algorithms ignore the incompleteness problem The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test The approach would work well only if the the corresponding testability demands were fulfilled A B C D a D c A = ax D: B = bx C = cx a,c,D fixed x - free a System Module c

42. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 42 Hierarchical Test Generation Approaches Top-down approach has been proposed to solve the test generation problem by deriving environmental constraints for low-level solutions. This method is more flexible since it does not narrow the search for the global test solution to pregenerated patterns for the system modules However the method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied Top-down approach: A B C D’ a’x d’x c’x A = a’x D’ = d’x C = c’x a’ c’ a’,c’,D’ fixed x - free System Module

43. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 43 Hierarchical Test Generation on DDs Single path activation in a single DD Data function R 1 * R 2 is tested Data path Decision Diagram Hierarhical test generation with DDs: Scanning test (defect-oriented) Control: y 1 y 2 y 3 y 4 = x032 Data: For all specified pairs of (R 1, R 2 ) HL Test program: Low level test data (constraints W)

44. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 44 Test Generation on High Level DDs y 4 y 3 y 1 R 1 +R 2 IN+ R 2 R 1 *R 2 IN*R 2 y 2 R 2 0 1 2 0 1 0 1 0 1  0 R 2 IN R 1 2 3 Multiple paths activation in a single DD Control function y 3 is tested Data path Decision Diagram High-level test generation with DDs: Conformity test (High-level faults) Control: For D = 0,1,2,3: y 1 y 2 y 3 y 4 = 00D2 Data: Solution of R 1 + R 2  IN  R 1  R 1 * R 2 Test program: Activating high-level faults:

45. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 45 Defect-Oriented Test Generation Test generation for a bridging fault: & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro D D D D D 1 1 1 1 Fault manifestation: W d = x 6 x 7 = 1: x 6 = 0, x 7 = 1, x 7 = D Fault propagation: x 2 = 1, x 1 = 1, b = 1, c = 1 Line justification: b = 1: x 5 = 0 y Component F(x 1,x 2,…,x n ) Defect WdWd Activate a path Bridge between leads 7 3 and 6 WdWd 0 1

46. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 46 Test Generation with SSBDDs & & & & & & & 1 2 3 4 5 6 7 7171 7272 7373 a b c d e y Macro 6 7373 1 2 5 7272 7171 y 0 1 Test pattern for the node 7 1 at the constraint W d = x 6 x 7 = 1: 1 2 3 4 5 6 7 y 1 1 0 0 1 1 Defect: dx 7 =1: x 7 =0 No fault: dx 7 =0: x 7 =1 Defect W d manifestation: W d = x 6 x 7 = 1: x 6 = 0, x 7 = 1, x 7 = D Functional Fault dx 7 propagation: x 1 = 1, x 2 = 1, x 5 = 0 Bridge between leads 7 and 6: (dx 7,W d ) (dx 7,W d )

47. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 47 Test Generation for Microprocessors I 1 :MVI A,DA  IN I 2 :MOV R,AR  A I 3 :MOV M,ROUT  R I 4 :MOV M,AOUT  A I 5 :MOV R,MR  IN I 6 :MOV A,MA  IN I 7 :ADD RA  A + R I 8 :ORA RA  A  R I 9 :ANA RA  A  R I 10 :CMA A,DA   A High-Level DDs for a microprocessor (example): Instruction set: IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor:

48. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 48 Test Generation for Microprocessors High-Level DD-based structure of the microprocessor (example): IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: OUT R A IN I

49. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 49 Test Generation for Microprocessors IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Scanning test program for adder: Instruction sequence T = I 5 (R)I 1 (A)I 7 I 4 for all needed pairs of (A,R) OUT I4I4 A I7I7 A R I1I1 IN(2) IN(1) R I5I5 Time: t t - 1 t - 2 t - 3 Observation Test Load

50. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 50 Test Generation for Microprocessors IR 3 A OUT 4 IA 2 R IN 5 R 1,3,4,6-10 IIN 1,6 A A 2,3,4,5 A + R 7 A  R 8 A  R 9  A 10 DD-model of the microprocessor: Conformity test program for decoder: Instruction sequence T = I 5 I 1 D I 4 for all D  I 1 - I 10  at given A,R,IN Data generation: Data IN,A,R are generated so that the values of all functions were different

51. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 51 Conclusions Physical defects can be formally mapped to the logic level by Boolean differential calculus Functional fault model is a universal means for mapping test results from lower levels to higher levels, giving a formal basis for hierarchical approaches to test generation and fault simulation Decision diagrams is a suitable tool which can be used successfully both, on the logic level, and also on higher register transfer or behavioral levels

52. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 52 References 1.S.Mourad, Y.Zorian. Principles of Testing Electronic Systems. J.Wiley & Sons, Inc. New York, 2000, 420 p. 2.M.L.Bushnell, V.D.Agrawal. Essentials of Electronic testing. Kluwer Acad. Publishers, 2000, 690 p. 3.M. Abramovici et. al. Digital Systems Testing & Testable Designs. Computer Science Press, 1995, 653 p. 4.S. Minato. Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publishers, 1996, 141 p. 5.R.Ubar. Test Synthesis with Alternative Graphs. IEEE Design and Test of Computers. Spring, 1996, pp.48-59. 6.J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. JETTA: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp. 213-226, 2000. 7.R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED’02, San Jose, California, March 26-28, 2001, pp.365-371. 8.T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation with Real Defects Coverage. Pergamon Press. J. of Microelectronics Reliability, Vol. 42, 2002, pp.1141-114.

53. Technical University Tallinn, ESTONIA Copyright 2000-2003 by Raimund Ubar 53 References European Projects: –EEMCN, FUTEG, ATSEC, SYTIC, VILAB, REASON, eVIKINGS II Special thanks to: –EU project IST-2000-30193 REASON –Cooperation partners: IISAS Bratislava, TU Warsaw –Colleagues: J.Raik, A.Jutman, E.Ivask, E.Orasson a.o. (TU Tallinn) Contact data: –Tallinn Technical University –Computer Engineering Department –Address: Raja tee 15, 12618 Tallinn, Estonia –Tel.: +372 620 2252, Fax: +372 620 2253 –E-mail: raiub@pld.ttu.ee –www.ttu.ee/ ˇ raiub/