1. ATtiny23131 A SEMINAR ON AVR MICROCONTROLLER ATtiny2313

2. ATtiny23132 Overview Features Features Peripheral Features Special Microcontroller Features Special Microcontroller Features AVR CPU CORE AVR CPU CORE AVR ATtiny2313 Memories AVR ATtiny2313 Memories System clock System clock Registers Registers USART USART Universal Serial Interface – USI Universal Serial Interface – USI

3. ATtiny23133 Features Utilizes the AVR® RISC Architecture Utilizes the AVR® RISC Architecture AVR – High-performance and Low-power RISC Architecture AVR – High-performance and Low-power RISC Architecture 120 Powerful Instructions – Most Single Clock Cycle Execution 120 Powerful Instructions – Most Single Clock Cycle Execution 32 General Purpose Working Registers 32 General Purpose Working Registers Fully Static Operation Fully Static Operation

4. ATtiny23134 AVR Peripherals USART USART – Serial communication with the PC SPI – Serial Peripheral Interface SPI – Serial Peripheral Interface – Synchronous serial communication ADC ADC – Analog – Digital Converter I/O Ports I/O Ports – General Purpose Input Output pins (GPIO)

5. ATtiny23135 Special Microcontroller Features debug WIRE On-chip Debugging In-System Programmable via SPI Port External and Internal Interrupt Sources Low-power Idle, Power-down, and Standby Modes Enhanced Power-on Reset Circuit Internal Calibrated Oscillator Special Microcontroller Features debug WIRE On-chip Debugging In-System Programmable via SPI Port External and Internal Interrupt Sources Low-power Idle, Power-down, and Standby Modes Enhanced Power-on Reset Circuit Internal Calibrated Oscillator

6. ATtiny23136 AVR Power Management Low Power operation – 15 mW @ 4 MHz Low Power operation – 15 mW @ 4 MHz Multiple Sleep Modes Multiple Sleep Modes – Sleep Modes: Shutdown unused components – Idle Mode – 6 mW CPU OFF, all peripherals ON CPU OFF, all peripherals ON CPU “woken up” by interrupts CPU “woken up” by interrupts – Power Down Mode – 75 mW CPU and most peripherals OFF CPU and most peripherals OFF External Interrupts, 2 Wire Interface, Watchdog ON External Interrupts, 2 Wire Interface, Watchdog ON – Power Save Mode – 120 mW Similar to Power Down Similar to Power Down Timer0 continues to run “asynchronously” Timer0 continues to run “asynchronously”

7. ATtiny23137 I/O and Packages – 18 Programmable I/O Lines – 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF Operating Voltages – 1.8 - 5.5V (ATtiny2313V) – 2.7 - 5.5V (ATtiny2313 ) Power-down Mode < 0.1 μA at 1.8VI/O and Packages – 18 Programmable I/O Lines – 20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF Operating Voltages – 1.8 - 5.5V (ATtiny2313V) – 2.7 - 5.5V (ATtiny2313 ) Power-down Mode < 0.1 μA at 1.8V

8. ATtiny23138 Pin Configuration

9. ATtiny23139 AVR CPU CORE The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

10. ATtiny231310 CPU CORE Functions Functions – Application Execution – Resource Management – Peripheral Interaction RISC Architecture RISC Architecture – 8 bit ALU/data-path – 128 Kb FLASH - Code – 4 Kb SRAM - Data – Multiple peripherals

11. ATtiny231311 AVR STATUS REGISTERAVR STATUS REGISTER

12. ATtiny231312 GENERAL PURPOSE REGISTERS

13. ATtiny231313 System Clock All the clocks need not be active at a given time. In order to reduce the power consumption, the clocks can be halted by using different modes. CPU CLOCK CPU CLOCK I/O CLOCK I/O CLOCK FLASH CLOCK FLASH CLOCK

14. ATtiny231314 CLOCK SOURCES EXTERNAL CLOCK EXTERNAL CLOCK CALIBRATED INTERNAL RC OSCILLATOR 4Mhz CALIBRATED INTERNAL RC OSCILLATOR 4Mhz CALIBRATED INTERNAL RC OSCILLATOR 8Mhz CALIBRATED INTERNAL RC OSCILLATOR 8Mhz WATCHDOG OSCILLATOR WATCHDOG OSCILLATOR CRYSTAL /CEREMIC OSCILLATOR CRYSTAL /CEREMIC OSCILLATOR

15. ATtiny231315 INTERRUPTS SOFTWARE INTERRUPTS SOFTWARE INTERRUPTS EXTERNAL INTERRUPTS EXTERNAL INTERRUPTS External interrupt contain registers: MCU CONTROL REGISTER MCU CONTROL REGISTER GERERAL INTERRUPT MASK REGISTER ( GIMSK) GERERAL INTERRUPT MASK REGISTER ( GIMSK) EXTERNAL INTERRUPT FLAG REGISTER ( EIFR) EXTERNAL INTERRUPT FLAG REGISTER ( EIFR) PIN CHANGE MASK REGISTER (PCMSK) PIN CHANGE MASK REGISTER (PCMSK)

16. ATtiny231316 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. The overriding signals may not be present in all port pins. The overriding signals are generated internally in the modules having the alternate function. Most port pins have alternate functions in addition to being general digital I/Os. The overriding signals may not be present in all port pins. The overriding signals are generated internally in the modules having the alternate function. PORT A PORT A PORT B PORT B PORT C PORT C

17. ATtiny231317 8-BIT TIMER/COUNTER Timer/counter is a general pupose 8-bit module with two independent output compare units. It allows program execution timing. timing. Two independent output compare units. Two independent output compare units. Clear timer on compare match. Clear timer on compare match. Frequency generator Frequency generator Interrupt sources Interrupt sources

18. ATtiny231318 USART The Universal Synchronous and Asynchronous serial Receiver and Transmitter highly flexible serial communication device. : Full Duplex Operation (Independent Serial Receive and Transmit Registers) Asynchronous or Synchronous Operation Master or Slave Clocked Synchronous Operation High Resolution Baud Rate Generator Odd or Even Parity Generation and Parity Check Supported by Hardware Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete Multi-processor Communication Mode

19. ATtiny231319 AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: The USART is fully compatible with the AVR UART regarding: Bit locations inside all USART Registers. Bit locations inside all USART Registers. Baud Rate Generation. Baud Rate Generation. Transmitter Operation. Transmitter Operation. Transmit Buffer Functionality. Transmit Buffer Functionality. Receiver Operation Receiver Operation

20. ATtiny231320 Universal Serial Interface The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code allows significantly higher transfer rates and uses less code space than solutions based on software only. Interrupts are space than solutions based on software only. Interrupts are included to minimize the processor load included to minimize the processor load

21. ATtiny231321 THANK YOU THANK YOU