1. ARM MIPS

4.  32 registers, each 32-bit wide. 30 are general purpose, R30(Hi) and R31(Low) are reserved for the results of long multiplication (64-bit result).

5.  The register file has three read ports. Reading is done asynchronously and the addresses of the registers to be read are provided by RA1, RA2 and RA3 (each 5-bit wide) while the data of these addressed registers are reflected on RD1, RD2 and RD3 (each 32-bit wide).

6.  Writing into the registers is done at the negative edge of a clock and is enabled by the write control signal. The address of the register to be written is supplied by WA (5-bit wide) and the data is provided by WD (32-bit wide).

8.  There are 32 32-bit registers in a MIPS datapath.  The register bank module includes  two read register address inputs (5-bits each),  one write register address input (5- bits),  a write-enable signal input (1-bit),  a write data input (32-bits), and  two read data outputs (32-bits).

9.  On the positive edge of the write-enable input, the register bank will update the contents of the register at the write address with whatever data is on the write data bus.  The read data outputs are output asynchronously – i.e. they are a function of the read register addresses.