1. Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang, Chin-Fang Shen, Wei-Chih Tseng NTU &Synopsys An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs ICCAD 2009

2. Introduction Overall Flow –Initial Setting –Ring-by-Ring routing –Routability Analysis & Refinement –Detailed Routing Experimental Result Conclusion Outline 2

3. The flip-chip package is a technique for connecting a die to an external circuitry such as package carriers or PCBs. The flip chip routing problem can be classified into two categories: –free-assignment routing problem. –pre-assignment routing problem. The pre-assignment problem has been shown to be much more difficult than the free-assignment one, but is more popular in real world designs. Introduction 3

4. [3, 4] presented the only pre-assignment routing algorithm in the literature. Based on integer linear programming (ILP), it adopts a two- stage technique of global routing followed by detailed routing. –ILP is typically very time-consuming. –misses some critical solution space with better solutions. Previous Work 4

5. Notations Problem Formulation 5 set of driver pads in driver pad ring set of bump pads in bump pad ring set of nets set of bump pad rings of the chip. set of driver pad rings of the chip.

6. The Single-Layer Pre-Assignment Flip-Chip Routing Problem: –Given D, B, and N, connect driver pads and bump pads according to a predefined netlist with wire width, wire spacing, and signal skew constraints so that no constraint is violated, and the total wirelength is minimized under the 100% routability guarantee. Problem Formulation 6

7. If drivers and bump pads are connected directly without detours, there will be a crossing. Therefore, the net sequence must be exchanged (b) on the driver pad side or (c) on the bump pad side to complete the routing. Overall Flow 7 X

8. Use v-pad (virtual pad) to represent the possible order of driver pads. Objective is to exchange the sequence of bump pads to be a subsequence of the possible sequence of driver pads so that driver pads and bump pads can be connected without any crossing. If there are multi-pin nets, we first decompose them as 2-pin nets, route the 2-pin nets, and merge them after the routing. Initial setting 8

9. String construction & weight computation Weighted Longest Common Subsequence(WLCS) Maximum Planar Subset of Chords(MPSC) Ring-by-Ring Routing 9

10. String construction & weight computation –Choosing a cut line so that the cut line does not have a crossing with a net, generate a linearly ordered string. Ring-by-Ring Routing 10 n 4 n 2 n 4 n 6 n 5 n 6 n 3 n 1 n 3 n 1 n 2 n 3

11. Weighted Longest Common Subsequence(WLCS) –only make “decisions” on whether a net needs a detour or not. Any real route is decided in the next step, the MPSC computation. Ring-by-Ring Routing 11 n 4 n 2 n 4 n 6 n 5 n 6 n 3 n 1 n 3 n 1 n 2 n 3 C 18 C 22 C 37 C 39 Weight2334

12. WLCS Ring-by-Ring Routing 12 n 4 n 2 n 4 n 6 n 5 n 6 n 3 n 1 n 3 n 1 n 2 n 3

13. MPSC Computation –minimize the number of nets needing detours outside the circle formed by the current ring and the preceding ring. –also route the nets from the preceding ring to proper positions along the current ring so that the sequence of bump pads can be consistent with the sequence of driver pads. Ring-by-Ring Routing 13

14. Routability Analysis & Refinement 14 d e & f c

15. To transform the topology routes into physical routes, we develop a two-phase detailed router to complete the routing : –In the first phase, a net is fragmented into a set of segments according to its passing points. Route the segments one by one in the clockwise order for each ring and make the routes as compacted as possible. –In the second phase, each segment of a net is combined, and then reroute the net in the counter-clockwise order to minimize the wirelength and the number of bends as well. Detailed routing 15

16. Experimental Result 16

17. Based on the concept of sequence exchange, we have proposed a very efficient flip-chip global-routing algorithm. Experimental results have shown that our router can achieve a 122X speedup with even better solution quality, compared with the state-of- the-art ILP-based flip-chip router. Conclusion 17