1. MODERN OPERATING SYSTEMS Third Edition ANDREW S. TANENBAUM Chapter 8 Multiple Processor Systems Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Lecture 12, 11 December 2012

2. Agenda 8.1 Multiprocessors 8.2 Multicomputers 8.3 Virtualization 8.4 Distributed Systems Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

3. About Moore’s Law Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Travel speed of light : in vacuum ~30 cm/nsec in optical fiber ~20 cm/nsec Other big challenge: heat dissipation So going from 1 GHz clock computer to 1 THz requires a radically different approach

4. Figure 8-1. (a) A shared-memory multiprocessor. (b) A message- passing multicomputer. (c) A wide area distributed system. 8.1 Multiple Processor Systems Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

5. Figure 8-2. Three bus-based multiprocessors. (a) Without caching. (b) With caching. (c) With caching and private memories. UMA Multiprocessors with Bus-Based Architectures Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 UMA: Uniform Memory Access

6. Figure 8-3. (a) An 8 × 8 crossbar switch. (b) An open crosspoint. (c) A closed crosspoint. UMA Multiprocessors using Crossbar Switches Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 n*n switches

7. Figure 8-4. (a) A 2 × 2 switch with two input lines, A and B, and two output lines, X and Y. (b) A message format. UMA Multiprocessors using Multistage Switching Networks (1) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 Used by the switch to send the message to X or Y

8. Figure 8-5. An omega switching network. UMA Multiprocessors using Multistage Switching Networks (2) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 (n/2) * ln n switches

9. NUMA Multiprocessors (1) Characteristics of NUMA machines: 1.There is a single address space visible to all CPUs. 2.Access to remote memory is via LOAD and STORE instructions. 3.Access to remote memory is slower than access to local memory. Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

10. Figure 8-6. (a) A 256-node directory-based multiprocessor. NUMA Multiprocessors (2) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

11. Figure 8-6. (b) Division of a 32-bit memory address into fields. (c) The directory at node 36. NUMA Multiprocessors (3) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

12. Figure 8-7. Partitioning multiprocessor memory among four CPUs, but sharing a single copy of the operating system code. 8.1.2 Multiprocessor OS Types: Each CPU Has Its Own Operating System Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 The boxes marked Data are the operating system’s private data for each CPU.

13. Figure 8-8. A master-slave multiprocessor model. Master-Slave Multiprocessors Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

14. Figure 8-9. The SMP multiprocessor model. Symmetric Multiprocessors Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

15. Figure 8-10. The TSL instruction can fail if the bus cannot be locked. These four steps show a sequence of events where the failure is demonstrated. Multiprocessor Synchronization (1) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 TSL = Test Set and Lock (atomic function for each CPU, but not for different CPUs !)

16. Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639 8.2 Multicomputers -Tightly coupled CPUs that do not share memory - Communication via message passing (send, receive) Alternative names: - Cluster computers - Cluster of workstation (COWS)

17. Figure 8-16. Various interconnect topologies. (a) A single switch. (b) A ring. (c) A grid. Interconnection Technology (1) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

18. Figure 8-16. Various interconnect topologies. (d) A double torus. (e) A cube. (f) A 4D hypercube. Interconnection Technology (2) Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

19. Figure 8-18. Position of the network interface boards in a multicomputer. Network Interfaces Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

20. Figure 8-19. (a) A blocking send call. Blocking (or Synchronous) Calls Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

21. Figure 8-19. (b) A nonblocking send call. Nonblocking (or Asynchronous) Calls Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

22. Figure 8-20. Steps in making a remote procedure call. The stubs are shaded gray. Remote Procedure Call Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

23. Figure 8-30. Positioning of middleware in a distributed system. 8.4 Distributed Systems Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

24. Figure 8-31. (a) Classic Ethernet. (b) Switched Ethernet. Ethernet Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639

25. Figure 8-32. A portion of the Internet. The Internet Tanenbaum, Modern Operating Systems 3 e, (c) 2008 Prentice-Hall, Inc. All rights reserved. 0-13-6006639