1. Randal E. Bryant adapted by Jason Fritts CS:APP2e CS:APP Chapter 4 Computer Architecture SequentialImplementation CS:APP Chapter 4 Computer Architecture SequentialImplementation http://csapp.cs.cmu.edu

2. – 2 – CS:APP2e Hardware Architecture - using Y86 ISA For learning aspects of hardware architecture design, we’ll be using the Y86 ISA x86 is a CISC language too complex for educational purposes Y86 Instruction Set Architecture a pseudo-language based on x86 (IA-32) similar state, but simpler set of instructions simpler instruction formats and addressing modes more RISC-like ISA than IA-32Format 1 – 6 bytes of information read from memory can determine instruction length from first byte

3. – 3 – CS:APP2e Y86 Instruction Set #1 Byte 012345 pushl rA A0 rA 8 jXX Dest 7 fn Dest popl rA B0 rA 8 call Dest 80 Dest cmovXX rA, rB 2 fnrArB irmovl V, rB 308 rB V rmmovl rA, D ( rB ) 40 rArB D mrmovl D ( rB ), rA 50 rArB D OPl rA, rB 6 fnrArB ret 90 nop 10 halt 00 rrmovl 70 cmovle 71 cmovl 72 cmove 73 cmovne 74 cmovge 75 cmovg 76

4. – 4 – CS:APP2e Y86 Instruction Set #2 Byte 012345 pushl rA A0 rA 8 jXX Dest 7 fn Dest popl rA B0 rA 8 call Dest 80 Dest cmovXX rA, rB 2 fnrArB irmovl V, rB 308 rB V rmmovl rA, D ( rB ) 40 rArB D mrmovl D ( rB ), rA 50 rArB D OPl rA, rB 6 fnrArB ret 90 nop 10 halt 00 addl 60 subl 61 andl 62 xorl 63

5. – 5 – CS:APP2e Y86 Instruction Set #3 Byte 012345 pushl rA A0 rA 8 jXX Dest 7 fn Dest popl rA B0 rA 8 call Dest 80 Dest rrmovl rA, rB 2 fnrArB irmovl V, rB 308 rB V rmmovl rA, D ( rB ) 40 rArB D mrmovl D ( rB ), rA 50 rArB D OPl rA, rB 6 fnrArB ret 90 nop 10 halt 00 jmp 70 jle 71 jl 72 je 73 jne 74 jge 75 jg 76

6. – 6 – CS:APP2e Encoding Registers Each register has 4-bit ID Same encoding as in IA32 Register ID 15 (0xF) indicates “no register” Will use this in our hardware design in multiple places %eax %ecx %edx %ebx %esi %edi %esp %ebp 0 1 2 3 6 7 4 5

7. – 7 – CS:APP2e Building Blocks Combinational Logic Compute Boolean functions of inputs Continuously respond to input changes Operate on data and implement control Storage Elements Store bits Addressable memories Non-addressable registers Loaded only as clock rises Register file Register file A B W dstW srcA valA srcB valB valW Clock ALUALU fun A B MUX 0 1 = Clock

8. – 8 – CS:APP2e Hardware Control Language Very simple hardware description language Can only express limited aspects of hardware operation Parts we want to explore and modify Data Types bool : Boolean a, b, c, … int : words A, B, C, … Does not specify word size---bytes, 32-bit words, …Statements bool a = bool-expr ; int A = int-expr ;

9. – 9 – CS:APP2e HCL Operations Classify by type of value returned Boolean Expressions Logic Operations a && b, a || b, !a Word Comparisons A == B, A != B, A = B, A > B Set Membership A in { B, C, D } »Same as A == B || A == C || A == D Word Expressions Case expressions [ a : A; b : B; c : C ] Evaluate test expressions a, b, c, … in sequence Return word expression A, B, C, … for first successful test

10. – 10 – CS:APP2e Datapath Implements the Fetch-Decode-Execute Cycle Fetch Fetch next instruction to be executed from memory PC holds the address of the next instruction to be executedDecode Decode instruction, and send control signals to parts of datapath Instr code and func code identify what instruction to execute Reg IDs identify what regs to read/write Immediates indicate what mem addr and/or non- register values to use Read register values from reg fileExecute Perform specified operation on the data Save results in register or memory Update the PC Fetch DecodeExecute

11. – 11 – CS:APP2e SEQ Hardware Structure State Program counter register (PC) Condition code register (CC) Register File Memories Access same memory space Data: for reading/writing program data Instruction: for reading instructions Instruction Flow Read instruction at address specified by PC Process through stages Update program counter Instruction memory Instruction memory PC increment PC increment CC ALU Data memory Data memory Fetch Decode Execute Memory Write back icode, ifun rA,rB valC Register file Register file AB M E Register file Register file AB M E PC valP srcA,srcB dstA,dstB valA,valB aluA,aluB Cnd valE Addr, Data valM PC valE,valM newPC

12. – 12 – CS:APP2e SEQ Stages Fetch Read instruction from instruction memoryDecode Read program registersExecute Compute value or addressMemory Read or write data Write Back Write program registersPC Update program counter Instruction memory Instruction memory PC increment PC increment CC ALU Data memory Data memory Fetch Decode Execute Memory Write back icode, ifun rA,rB valC Register file Register file AB M E Register file Register file AB M E PC valP srcA,srcB dstA,dstB valA,valB aluA,aluB Cnd valE Addr, Data valM PC valE,valM newPC

13. – 13 – CS:APP2e Instruction Decoding Instruction Format Instruction byteicode:ifun Optional register byterA:rB Optional constant wordvalC 50 rArB D icode ifun rA rB valC Optional

14. – 14 – CS:APP2e Executing Arith./Logical Operation Fetch Read 2 bytesDecode Read operand registersExecute Perform operation Set condition codesMemory Do nothing Write back Update register PC Update Increment PC by 2 OPl rA, rB 6 fn rArB

15. – 15 – CS:APP2e Stage Computation: Arith/Log. Ops Formulate instruction execution as sequence of simple steps Use same general form for all instructions OPl rA, rB icode:ifun  M 1 [PC] rA:rB  M 1 [PC+1] valP  PC+2 Fetch Read instruction byte Read register byte Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB OP valA Set CC Execute Perform ALU operation Set condition code register Memory R[rB]  valE Write back Write back result PC  valP PC update Update PC

16. – 16 – CS:APP2e Executing rmmovl Fetch Read 6 bytesDecode Read operand registersExecute Compute effective addressMemory Write to memory Write back Do nothing PC Update Increment PC by 6 rmmovl rA, D ( rB) 40 rA rB D

17. – 17 – CS:APP2e Stage Computation: rmmovl Use ALU for address computation rmmovl rA, D(rB) icode:ifun  M 1 [PC] rA:rB  M 1 [PC+1] valC  M 4 [PC+2] valP  PC+6 Fetch Read instruction byte Read register byte Read displacement D Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB + valC Execute Compute effective address M 4 [valE]  valA Memory Write value to memory Write back PC  valP PC update Update PC

18. – 18 – CS:APP2e Executing popl Fetch Read 2 bytesDecode Read stack pointerExecute Increment stack pointer by 4Memory Read from old stack pointer Write back Update stack pointer Write result to register PC Update Increment PC by 2 popl rA b0 rA F

19. – 19 – CS:APP2e Stage Computation: popl Use ALU to increment stack pointer Must update two registers Popped value New stack pointer popl rA icode:ifun  M 1 [PC] rA:rB  M 1 [PC+1] valP  PC+2 Fetch Read instruction byte Read register byte Compute next PC valA  R[ %esp ] valB  R [ %esp ] Decode Read stack pointer valE  valB + 4 Execute Increment stack pointer valM  M 4 [valA] Memory Read from stack R[ %esp ]  valE R[rA]  valM Write back Update stack pointer Write back result PC  valP PC update Update PC

20. – 20 – CS:APP2e Executing Jumps Fetch Read 5 bytes Increment PC by 5Decode Do nothingExecute Determine whether to take branch based on jump condition and condition codesMemory Do nothing Write back Do nothing PC Update Set PC to Dest if branch taken or to incremented PC if not branch jXX Dest 7 fn Dest XX fall thru: XX target: Not taken Taken

21. – 21 – CS:APP2e Stage Computation: Jumps Compute both addresses Choose based on setting of condition codes and branch condition jXX Dest icode:ifun  M 1 [PC] valC  M 4 [PC+1] valP  PC+5 Fetch Read instruction byte Read destination address Fall through address Decode Cnd  Cond(CC,ifun) Execute Take branch? Memory Write back PC  Cnd ? valC : valP PC update Update PC

22. – 22 – CS:APP2e Executing call Fetch Read 5 bytes Increment PC by 5Decode Read stack pointerExecute Decrement stack pointer by 4Memory Write incremented PC to new value of stack pointer Write back Update stack pointer PC Update Set PC to Dest call Dest 80 Dest XX return: XX target:

23. – 23 – CS:APP2e Stage Computation: call Use ALU to decrement stack pointer Store incremented PC call Dest icode:ifun  M 1 [PC] valC  M 4 [PC+1] valP  PC+5 Fetch Read instruction byte Read destination address Compute return point valB  R[ %esp ] Decode Read stack pointer valE  valB + –4 Execute Decrement stack pointer M 4 [valE]  valP Memory Write return value on stack R[ %esp ]  valE Write back Update stack pointer PC  valC PC update Set PC to destination

24. – 24 – CS:APP2e Executing ret Fetch Read 1 byteDecode Read stack pointerExecute Increment stack pointer by 4Memory Read return address from old stack pointer Write back Update stack pointer PC Update Set PC to return address ret 90XX return:

25. – 25 – CS:APP2e Stage Computation: ret Use ALU to increment stack pointer Read return address from memory ret icode:ifun  M 1 [PC] Fetch Read instruction byte valA  R[ %esp ] valB  R[ %esp ] Decode Read operand stack pointer valE  valB + 4 Execute Increment stack pointer valM  M 4 [valA] Memory Read return address R[ %esp ]  valE Write back Update stack pointer PC  valM PC update Set PC to return address

26. – 26 – CS:APP2e Computation Steps All instructions follow same general pattern Differ in what gets computed on each step OPl rA, rB icode:ifun  M 1 [PC] rA:rB  M 1 [PC+1] valP  PC+2 Fetch Read instruction byte Read register byte [Read constant word] Compute next PC valA  R[rA] valB  R[rB] Decode Read operand A Read operand B valE  valB OP valA Set CC Execute Perform ALU operation Set condition code register Memory [Memory read/write] R[rB]  valE Write back Write back ALU result [Write back memory result] PC  valP PC update Update PC icode,ifun rA,rB valC valP valA, srcA valB, srcB valE Cond code valM dstE dstM PC

27. – 27 – CS:APP2e Computation Steps All instructions follow same general pattern Differ in what gets computed on each step call Dest Fetch Decode Execute Memory Write back PC update icode,ifun rA,rB valC valP valA, srcA valB, srcB valE Cond code valM dstE dstM PC icode:ifun  M 1 [PC] valC  M 4 [PC+1] valP  PC+5 valB  R[ %esp ] valE  valB + –4 M 4 [valE]  valP R[ %esp ]  valE PC  valC Read instruction byte [Read register byte] Read constant word Compute next PC [Read operand A] Read operand B Perform ALU operation [Set condition code reg.] [Memory read/write] [Write back ALU result] Write back memory result Update PC

28. – 28 – CS:APP2e Computed Values Fetch icodeInstruction code ifunInstruction function rAInstr. Register A rBInstr. Register B valCInstruction constant valPIncremented PCDecode srcARegister ID A srcBRegister ID B dstEDestination Register E dstMDestination Register M valARegister value A valBRegister value BExecute valEALU result CndBranch/move flagMemory valMValue from memory

29. – 29 – CS:APP2e SEQ Hardware Key Blue boxes: predesigned hardware blocks E.g., memories, ALU Gray boxes: control logic Describe in HCL White ovals: labels for signals Thick lines: 32-bit word values Thin lines: 4-8 bit values Dotted lines: 1-bit values

30. – 30 – CS:APP2e Fetch Logic Predefined Blocks PC: Register containing PC Instruction memory: Read 6 bytes (PC to PC+5) Signal invalid address Split: Divide instruction byte into icode and ifun Align: Get fields for rA, rB, and valC Instruction memory Instruction memory PC increment PC increment rBicodeifunrA PC valCvalP Need regids Need valC Instr valid Align Split Bytes 1-5Byte 0 imem_error icodeifun

31. – 31 – CS:APP2e Fetch Logic Control Logic Instr. Valid: Is this instruction valid? icode, ifun: Generate no-op if invalid address Need regids: Does this instruction have a register byte? Need valC: Does this instruction have a constant word? Instruction memory Instruction memory PC increment PC increment rBicodeifunrA PC valCvalP Need regids Need valC Instr valid Align Split Bytes 1-5Byte 0 imem_error icodeifun

32. – 32 – CS:APP2e Fetch Control Logic in HCL # Determine instruction code int icode = [ imem_error: INOP; 1: imem_icode; ]; # Determine instruction function int ifun = [ imem_error: FNONE; 1: imem_ifun; ]; Instruction memory Instruction memory PC Split Byte 0 imem_error icodeifun

33. – 33 – CS:APP2e Fetch Control Logic in HCL bool need_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }; bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL }; pushl rA A0 rA 8 jXX Dest 7 fn Dest popl rA B0 rA 8 call Dest 80 Dest cmovXX rA, rB 2 fnrArB irmovl V, rB 308 rB V rmmovl rA, D ( rB ) 40 rArB D mrmovl D ( rB ), rA 50 rArB D OPl rA, rB 6 fnrArB ret 90 nop 10 halt 00

34. – 34 – CS:APP2e Decode Logic Register File Read ports A, B Write ports E, M Addresses are register IDs or 15 (0xF) (no access) Control Logic srcA, srcB: read port addresses dstE, dstM: write port addresses rB dstEdstMsrcAsrcB Register file Register file AB M E dstEdstMsrcAsrcB icoderA valBvalAvalEvalMCndSignals Cnd: Indicate whether or not to perform conditional move Computed in Execute stage

35. – 35 – CS:APP2e A Source int srcA = [ icode in { IRRMOVL, IRMMOVL, IOPL, IPUSHL } : rA; icode in { IPOPL, IRET } : RESP; 1 : RNONE; # Don't need register ]; cmovXX rA, rB valA  R[rA] Decode Read operand A rmmovl rA, D(rB) valA  R[rA] Decode Read operand A popl rA valA  R[ %esp ] Decode Read stack pointer jXX Dest Decode No operand call Dest valA  R[ %esp ] Decode Read stack pointer ret Decode No operand OPl rA, rB valA  R[rA] Decode Read operand A

36. – 36 – CS:APP2e E Desti- nation int dstE = [ icode in { IRRMOVL } && Cnd : rB; icode in { IIRMOVL, IOPL} : rB; icode in { IPUSHL, IPOPL, ICALL, IRET } : RESP; 1 : RNONE; # Don't write any register ]; None R[ %esp ]  valE Update stack pointer None R[rB]  valE cmovXX rA, rB Write-back rmmovl rA, D(rB) popl rA jXX Dest call Dest ret Write-back Conditionally write back result R[ %esp ]  valE Update stack pointer R[ %esp ]  valE Update stack pointer R[rB]  valE OPl rA, rB Write-back Write back result

37. – 37 – CS:APP2e Execute Logic Units ALU Implements 4 required functions Generates condition code values CC Register with 3 condition code bits cond Computes conditional jump/move flag Control Logic Set CC: Should condition code register be loaded? ALU A: Input A to ALU ALU B: Input B to ALU ALU fun: What function should ALU compute? CC ALU A ALU B ALU fun. Cnd icodeifunvalCvalBvalA valE Set CC cond

38. – 38 – CS:APP2e ALU A Input int aluA = [ icode in { IRRMOVL, IOPL } : valA; icode in { IIRMOVL, IRMMOVL, IMRMOVL } : valC; icode in { ICALL, IPUSHL } : -4; icode in { IRET, IPOPL } : 4; # Other instructions don't need ALU ]; valE  valB + –4 Decrement stack pointer No operation valE  valB + 4 Increment stack pointer valE  valB + valC Compute effective address valE  0 + valA Pass valA through ALU cmovXX rA, rB Execute rmmovl rA, D(rB) popl rA jXX Dest call Dest ret Execute valE  valB + 4 Increment stack pointer valE  valB OP valA Perform ALU operation OPl rA, rB Execute

39. – 39 – CS:APP2e ALU Oper- ation int alufun = [ icode == IOPL : ifun; 1 : ALUADD; ]; valE  valB + –4 Decrement stack pointer No operation valE  valB + 4 Increment stack pointer valE  valB + valC Compute effective address valE  0 + valA Pass valA through ALU cmovXX rA, rB Execute rmmovl rA, D(rB) popl rA jXX Dest call Dest ret Execute valE  valB + 4 Increment stack pointer valE  valB OP valA Perform ALU operation OPl rA, rB Execute

40. – 40 – CS:APP2e Memory Logic Memory Reads or writes memory word Control Logic stat: What is instruction status? Mem. read: should word be read? Mem. write: should word be written? Mem. addr.: Select address Mem. data.: Select data Data memory Data memory Mem. read Mem. addr read write data out Mem. data valE valM valAvalP Mem. write data in icode Stat dmem_error instr_valid imem_error stat

41. – 41 – CS:APP2e Instruction Status Control Logic stat: What is instruction status? Data memory Data memory Mem. read Mem. addr read write data out Mem. data valE valM valAvalP Mem. write data in icode Stat dmem_error instr_valid imem_error stat ## Determine instruction status int Stat = [ imem_error || dmem_error : SADR; !instr_valid: SINS; icode == IHALT : SHLT; 1 : SAOK; ];

42. – 42 – CS:APP2e Memory Address OPl rA, rB Memory rmmovl rA, D(rB) popl rA jXX Dest call Dest ret No operation M 4 [valE]  valA Memory Write value to memory valM  M 4 [valA] Memory Read from stack M 4 [valE]  valP Memory Write return value on stack valM  M 4 [valA] Memory Read return address Memory No operation int mem_addr = [ icode in { IRMMOVL, IPUSHL, ICALL, IMRMOVL } : valE; icode in { IPOPL, IRET } : valA; # Other instructions don't need address ];

43. – 43 – CS:APP2e Memory Read OPl rA, rB Memory rmmovl rA, D(rB) popl rA jXX Dest call Dest ret No operation M 4 [valE]  valA Memory Write value to memory valM  M 4 [valA] Memory Read from stack M 4 [valE]  valP Memory Write return value on stack valM  M 4 [valA] Memory Read return address Memory No operation bool mem_read = icode in { IMRMOVL, IPOPL, IRET };

44. – 44 – CS:APP2e PC Update Logic New PC Select next value of PC New PC CndicodevalCvalPvalM PC

45. – 45 – CS:APP2e PC Update OPl rA, rB rmmovl rA, D(rB) popl rA jXX Dest call Dest ret PC  valP PC update Update PC PC  valP PC update Update PC PC  valP PC update Update PC PC  Cnd ? valC : valP PC update Update PC PC  valC PC update Set PC to destination PC  valM PC update Set PC to return address int new_pc = [ icode == ICALL : valC; icode == IJXX && Cnd : valC; icode == IRET : valM; 1 : valP; ];

46. – 46 – CS:APP2e SEQ Operation State PC register Cond. Code register Data memory Register file All updated as clock rises Combinational Logic ALU Control logic Memory reads Instruction memory Register file Data memory

47. – 47 – CS:APP2e SEQ Operation #2 state set according to second irmovl instruction combinational logic starting to react to state changes

48. – 48 – CS:APP2e SEQ Operation #3 state set according to second irmovl instruction combinational logic generates results for addl instruction

49. – 49 – CS:APP2e SEQ Operation #4 state set according to addl instruction combinational logic starting to react to state changes

50. – 50 – CS:APP2e SEQ Operation #5 state set according to addl instruction combinational logic generates results for je instruction

51. – 51 – CS:APP2e SEQ Summary Implementation Express every instruction as series of simple steps Follow same general flow for each instruction type Assemble registers, memories, predesigned combinational blocks Connect with control logicLimitations Too slow to be practical In one cycle, must propagate through instruction memory, register file, ALU, and data memory Would need to run clock very slowly Hardware units only active for fraction of clock cycle