1. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU 102-1 Under-Graduate Project Improving Timing, Area, and Power Speaker: 黃乃珊 Adviser: Prof. An-Yeu Wu Date: 2013/12/12

2. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 2 Introduction  When design in RTL, the designer need to be aware of timing, area and power issues.  Meeting timing is the most critical goal in design. Only optimize for power or area after timing is met.  Synthesis tools operate in gate level, and cannot resolve all timing, area and power issues.

3. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 3 Timing Issues  Timing v.s. Performance  Latency  How long does it take to complete a particular operation?  Unit : ns, us, ms  Throughput  How many operations can be completed per second?  Unit : Mbps, Gbps Input 1bit output Throughput = 1bit/clock cycle Latency = 2 clock cycles

4. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 4 Timing Requirement  To fit system throughput, the timing (clock period) must be smaller than some value.  In IC design industry, the design must meet timing with margin, and using worst-case library model.

5. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 5 How to Improve Timing?  While your clock cycle time does not fit system specification  Pipelining : Exploits temporal parallelism  Reduce the clock cycle time (clock period)  Insert pipeline registers without changing coherence of the data.  Parallel skill  Decrease data flow of your design

6. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 6 Pipelining original 2-stage pipelining

7. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 7 Example 1 : Simple Circuit original 3-stage pipelining Critical path = 3 adders Critical path = 1 adders

8. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 8 Example 2 : Pipelined 16-bit Adder

9. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 9 Parallel Processing original Parallel processing

10. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 10 Area Issues  Area = Cost.  During the design process, the designer should be “area aware”.  Resource sharing

11. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 11 Power Consumption in CMOS  Low power design is more and more important in today’s chip design due to heat dissipation, packaging, and portability needs.  Power Consumption  N node : switching activity  f clock : clock frequency  C L : node capacitance  V dd : power supply voltage

12. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 12 Strategy for Low-Power Design (1/2)  V dd is technology-dependent.  Pipelining  Parallel processing  Execute tasks concurrently to improve throughput  Increase the system’s overall sampling rate  Incorporates multiple copies of hardware  C L can only be minimized by back-end design.  Optimize f clock and N node are the most practical power reduction techniques.

13. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 13  Reducing Clock Frequency  Design with clock rate that is ‘just right’  Clock Gating  Reducing switching activity  Avoid unnecessary circuit switching  Reducing switching activity at I/O pins  Use simple hardware if it gets the job done Strategy for Low-Power Design (2/2)

14. ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P. 14 Example : Multiplier original Low-power design