UBI >> Contents Lecture 5 Sigma-Delta (SD) converter, Slope converter & Comparator_A MSP430 Teaching Materials Texas Instruments Incorporated University.

UBI >> Contents Lecture 5 Sigma-Delta (SD) converter, Slope converter & Comparator_A MSP430 Teaching Materials Texas Instruments Incorporated University of Beira Interior (PT) Pedro Dinis Gaspar, António Espírito Santo, Bruno Ribeiro, Humberto Santos University of Beira Interior, Electromechanical Engineering Department www.msp430.ubi.pt Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt

UBI >> Contents 2 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Contents (1/2)  Sigma-Delta (SD) converter  Introduction to Sigma-Delta ADC : Introduction to Sigma-Delta ADC Delta modulator Digital filter Decimation digital filter  MSP430 SD16(A) – Sigma-Delta ADC MSP430 SD16(A) – Sigma-Delta ADC  Slope converter  Comparator-Based Slope ADC: Single- and dual- slope ADC Resistive sensors measurements Voltage measurements

UBI >> Contents 3 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Contents (2/2)  Comparator_A  Introduction to Comparator_A Introduction to Comparator_A  Features Features  Voltage reference generator Voltage reference generator  Comparator_A interrupts Comparator_A interrupts  Comparator_A registers Comparator_A registers

UBI >> Contents 4 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Sigma-Delta ADC Introduction (1/8)  Sigma-Delta (SD) converter determines the digital word: By oversampling the input signal using sigma-delta modulation; Applying digital filtering; Reducing data rate by collecting modulator output bits (decimation).

UBI >> Contents 5 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Sigma-Delta ADC Introduction (2/8)  Delta modulator:  Quantizes the difference between the current analogue input signal and the average of the previous samples.  Example: 1st order modulator (simplest form): Quantization (comparator): Output={1,0} if Input={+,-} Demodulator (integrator - 1 bit DAC): Output={ ,  } if Input={1,0}.

UBI >> Contents 6 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Sigma-Delta ADC Introduction (3/8)  Delta modulator:  Density of “1’s" at the modulator OUT is proportional to IN signal: Increasing IN, the comparator generates a greater number of “1’s"; Decreasing IN, the comparator generates a lesser number of “1’s".  By summing the error voltage, the integrator acts as a: Lowpass filter for the input signal; Highpass filter for the quantization noise.

UBI >> Contents 7 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Sigma-Delta ADC Introduction (4/8)  Delta modulator:  Most quantization noise is pushed into higher frequencies;  Oversampling changes noise distribution (but not total noise);  Quantization noise limits the dynamic range of the ADC;  Noise is the “round-off” error of analogue signal quantization.

UBI >> Contents 8 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Sigma-Delta ADC Introduction (5/8)  Digital Filter:  Averages the 1-bit data stream;  Improves the analogue to digital conversion resolution;  Removes quantization noise outside the band of interest;  Determines signal bandwidth, settling time and stopband rejection.

UBI >> Contents 9 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Sigma-Delta ADC Introduction (6/8)  Digital Filter:  SD converters: widely used lowpass filter: Sinc³ or Sinc 5 types.

UBI >> Contents 11 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Sigma-Delta ADC Introduction (8/8)  Decimation Digital Filter:  Decimation: Reduces the sampling rate down from the oversampling rate without losing information (eliminates redundant data);  Using the Nyquist theorem (f sample > 2f input ) and the oversampling at the delta modulator, the input signal can be reliably reconstructed without distortion.

UBI >> Contents 12 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) (1/2) Introduction  Applications MSP430 devices with up to 7 SD ADCs:  Portable medical (F42xx and FG42xx);  Energy metering (FE42x(A), F47xx, F471xx);  Generic applications (F42x and F20x3).  SD16_A: eZ430-F2013 hardware development tool;  SD16_A supports:  16-bit SD core;  Reference generator;  External analogue inputs;  Internal V CC sense;  Integrated temperature sensor.

UBI >> Contents 14 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) SD16_A Features  16-bit sigma-delta architecture;  Up to eight multiplexed differential analogue inputs per channel;  Software selectable on-chip reference voltage generation (1.2 V);  Software selectable internal or external reference;  Built-in temperature sensor;  Up to 1.1 MHz modulator input frequency;  Selectable low-power conversion mode.

UBI >> Contents 15 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) 16 bit SD ADC core  The analogue-to-digital conversion is performed by a 1-bit second-order oversampling sigma-delta modulator;  A single-bit comparator within the modulator quantizes the input signal with the modulator frequency, f M ;  The resulting 1-bit data stream is averaged by the digital decimation filter (comb type filter with selectable oversampling) for the conversion result;  The decimation filter has ratios of up to 1024. Additional filtering can be done in software.

UBI >> Contents 16 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) Analogue Input Range and PGA  The full-scale (FS) input voltage range for each analogue input pair is dependent on the gain setting of the PGA (= 1, 2, 4, 8, 16 & 32x);  The maximum FS range is ±V FS :

UBI >> Contents 17 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) Voltage Reference Generator  Voltage reference options:  Internal reference (1.2 V): SD16REFON=1, SD16VMIDON=0;  External reference: SD16REFON=0, SD16VMIDON=0;  Internal refeference, with reference with buffered output: SD16REFON=1, SD16VMIDON=1;  To reduce noise it is recommended to connect an external 100-nF capacitor from V REF to AV SS.

UBI >> Contents 18 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) Analogue Input Pair Selection  The SD16_A can convert up to 8 differential input pairs multiplexed into the PGA;  The available analogue input pairs are:  A0-A4: External to the device;  A5: Resistive divider to measure the supply voltage (AV CC /11);  A6: Internal temperature sensor;  A7: Offset shunt (used for calibration of SD16_A input PGA offset measurement).

UBI >> Contents 19 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) Analogue Input Step Response  Sinc 3 comb digital filter needs 3 data-word periods to settle;  SD16INTDLY = 00h, conversion interrupt requests do not begin until the 4th conversion after a start condition.

UBI >> Contents 20 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) Digital Filter  Processes the 1-bit data stream from the modulator using a Sinc 3 comb digital filter;  Take into consideration that: Oversampling rate is given by: OSR = f M /f S ; The first filter notch is at: f S = f M /OSR;  Modify the notch frequency adjustment with: SD16SSELx and SD16DIVx: Change f M ; SD16OSRx and SD16XOSR bits: Change OSR.  Number of output bits depends on the OSR and number format, ranging from 15 to 30 bits.

UBI >> Contents 21 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) Output Data Format  Selected with SD16DF and SD16UNI bits:  Two’s complement;  Offset binary;  Unipolar. SD16UNI = 0SD16UNI = 0SD16UNI = 1 SD16DF = 0SD16DF = 1SD16DF = 0

UBI >> Contents 22 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) (1/2) Conversion modes  Single conversion:  The channel is converted once (SD16SNGL = 1);  Starts when SD16SC = 1;  After conversion completion: SD16SC = 0;  Clearing SD16SC before the conversion is completed: Immediately stops conversion of the channel; Powers down the channel; Turns off the corresponding digital filter; The value in SD16MEM0 can change.

UBI >> Contents 23 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) (2/2) Conversion modes  Continuous conversion:  The channel is converted continuously (SD16SNGL = 0);  Starts when SD16SC = 1;  Stops when SD16SC = 0 (cleared by software);  Clearing SD16SC before the conversion is complete has the same effect as a single conversion.

UBI >> Contents 24 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) Integrated temperature sensor  Configured when:  Analogue input pair SD16INCHx = 110;  SD16REFON = 1;  SD16VMIDON = 1 (if is used an external reference for other analogue input pair).  The typical temperature sensor transfer function: V Sensor,typ = T CSensor (273 + T[ºC]) + V Offset, Sensor [mV]

UBI >> Contents 25 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) SD16_A interrupts  Two interrupt sources for each ADC channel:  SD16 Interrupt Flag (SD16IFG):  SD16IFG = 1: SD16MEM0 memory register is written with a conversion result;  An interrupt request requires: Corresponding SD16IE = 1; GIE = 1.  SD16 Overflow Interrupt Flag (SD16OVIFG):  SD16OVIFG = 1: conversion result is written to SD16MEM0 location before the previous conversion result was read.

UBI >> Contents 26 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) Interrupt vector generator (SD16IV)  Used to determine which enabled SD16_A interrupt source requested an interrupt;  Considerations: The highest priority enabled interrupt generates a number in the SD16IV register (evaluated or added to the program counter to automatically call the appropriate routine); Any access, read or write, of the SD16IV register has no effect on the SD16OVIFG or SD16IFG flags; SD16IFG flags are reset by reading the SD16MEM0 register or by clearing the flags in software; SD16OVIFG bits can only be reset by software.

UBI >> Contents 31 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt SD16(A) (5/5) Registers  SD16MEM0, SD16_A Conversion Memory Register  The 16-bit SD16MEMx register stores the conversion results. Depending on the SD16LSBACC bit state, it holds the upper or lower 16 bits of the digital filter output.  SD16AE, SD16_A Analogue Input Enable Register  8 bits SD16AE = 1 to enable the corresponding external analogue input (MSB: A7 to LSB: A0).  SD16IV, SD16_A Interrupt Vector Register  The contents of bits 1 to 4 of the 16 bits SD16IV indicate the interrupt source. According to their priority: SD16IV = 002hSD16MEMx overflow; SD16IV = 004hSD16_A Interrupt. For SD16IV = 000h No interrupt pending. From SD16IV = 006h to =010h (lowest) to interrupt source are reserved.

UBI >> Contents 32 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Single and Dual Slope ADC (1/3)  Single Slope architecture:  The simplest form of analogue-to-digital converter uses integration;  Method: Integration of unknown input voltage; Value comparison with a known reference value; The time it takes for the two voltages to become equal is proportional to the unknown voltage.  Drawbacks: The accuracy of this method is dependent on the tolerance of the passive elements (resistors and capacitors), which varies with the environment, resulting in low measurement repeatability.

UBI >> Contents 33 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Single and Dual Slope ADC (1/3)  Dual Slope architecture:  Overcomes the difficulties of the single slope method;  Method: Unknown V input integration, for a fixed time, t int ; Back-integration of known V REF for a variable time, t back_int. t int

UBI >> Contents 34 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Single and Dual Slope ADC (3/3)  The dual slope method requires:  Switch;  Clock;  Timer;  Comparator.  Resolution: depends on the clock frequency and ramp duration;  Some MSP430 devices have no true ADC, but they do have analogue comparator module (comparator_A) that can be used to implement a low power slope ADC;  Comparator_A is present on the MSP430FG4618 (Experimenter’s board).

UBI >> Contents 35 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Introduction to Comparator_A (1/2)  Comparator_A module is primary designed to support:  Low cost precision slope A/D conversions; Resistance measurement; Voltage measurement; Current measurement; Capacitance measurements.. Requires few external components;  Battery-voltage supervision;  Monitoring of external analogue signals.  It is used on the FG4618 device (Experimenter’s board).

UBI >> Contents 37 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Comparator_A Features  Comparator_A features:  Multiplexed inverting and non-inverting inputs;  Software selectable low-pass filter (RC) for the output;  Outputs: Timer_A capture input; Interrupt (one interrupt vector with enable): CAIFG; External: GPIO.  Software control of the port input buffer;  Selectable references, external or internal (reference voltage generator): V CAREF = 0.25 V CC ; V CAREF = 0.5 V CC ; V CAREF = ~0.55 V (diode);  Comparator and reference generator can be powered down.

UBI >> Contents 38 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Comparator_A components  Comparator:  Compares the analogue voltages at the (+) and (–) input terminals (CA0 and CA1 for a non-inverting topology);  The comparator output: CAOUT = 1: CA0 > CA1; CAOUT = 0: CA0 < CA1 and CAON = 0 (switched off).  Analogue input switches (selected with P2CAx bits):  Individually connect or disconnect the two comparator input terminals to associated port pins.  Output filter (CAF bit):  Use the internal low pass filter to reduce errors (in accuracy and resolution) associated with comparator oscillation.

UBI >> Contents 39 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Comparator_A interrupts  One interrupt flag, CAIFG, and one interrupt vector are associated with Comparator_A;  Condition for an interrupt:  CAIFG = 1: Rising or falling edge at comparator output (CAIES bits); Interrupt request when CAIE = 1 and GIE = 1.  CAIFG = 0: Interrupt request serviced; Reset by software.

UBI >> Contents 40 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Comparator_A (1/2) Registers  CACTL1, Comparator_A Control Register 1 BitDescription 7CAEXComparator_A exchange: CAEX = 1Exchanges the comparator inputs and inverts the comparator output. 6CARSELComparator_A reference: CAEX = 0:CAEX = 1: CARSEL = 0V CAREF in + terminalV CAREF in - terminal CARSEL = 1V CAREF in - terminalV CAREF in + terminal 5-4CAREFxComparator_A voltage reference: CAREF1 CAREF0 = 00External (Internal reference off) CAREF1 CAREF0 = 01V CAREF = 0.25 V CC CAREF1 CAREF0 = 10V CAREF = 0.5 V CC CAREF1 CAREF0 = 11V CAREF = 0.55 V (Diode reference) 3CAONComparator_A on when CAON = 1 2CAIESComparator_A interrupt edge: CAIES = 0Rising edge CAIES = 1Falling edge 1CAIEComparator_A interrupt enable when CAIE = 1 0CAIFGThe Comparator_A interrupt flag, CAIFG = 1 when an interrupt is pending

UBI >> Contents 41 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Comparator_A (2/2) Registers  CACTL2, Comparator_A Control Register 2  CAPD, Comparator_A Port Disable Register  The 8-bit CAPD register allows individual enable or disable of each P1.x pin buffer, when the corresponding CAPDx = 0 or CAPDx = 1 values respectively are configured.

UBI >> Contents 42 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Resistive Sensors Measurements (1/4)  Comparator_A can be used to measure resistive elements using single slope A/D conversion;  Thermistor: Resistor with R M varying according to T;  Schematic diagram of the measurement system: CMCM

UBI >> Contents 43 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Resistive Sensors Measurements (2/4)  MSP430 configuration:  2 digital I/O pins (Px.x; Px.y): Charge and discharge C M ;  I/O set to output high (V CC ) to charge C M, reset to discharge;  I/O switched to high-Z input with CAPDx set when not in use;  One output charges and discharges the capacitor via R REF ;  The other output discharges capacitor via R M ;  (+) terminal is connected to the + terminal of the capacitor;  (–) terminal is connected to ref. level (ex. V CAREF =0.25xV CC );  An output filter should be used to minimize switching noise;  CAOUT used to gate Timer_A CCI1B, capturing t CM_discharge.

UBI >> Contents 44 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Resistive Sensors Measurements (3/4)  Ratiometric conversion principle:  Charge/Discharge timing for temperature measurement system:

UBI >> Contents 45 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Resistive Sensors Measurements (4/4)  Slope resistance measurement considerations:  Measurement as accurate as R REF ;  V CC independent;  Resolution based on number of maximum counts;  Precharge of C M impacts accuracy (although there are methods to avoid errors by precharge);  Slope measurement time duration is a function of RC;

UBI >> Contents 46 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Voltage Measurements (1/3)  Comparator_A module’s application: Voltage measurement using single slope A/D conversion;  Relies on the charge/discharge of C:  Capacitor charge: V SS < V M < V CAREF ;  Capacitor discharge: V CAREF < V M < V SS ;  Time capture to crossing using Timer_A (TACCR1); 1st: Compare to V CAREF ; 2nd: Compare to V M.

UBI >> Contents 47 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Voltage Measurements (2/3)  Voltage conversion and timing depends on:  1 Measurement: V REF must be stable; RC tolerances influence measurements.  2 Measurements:; Same approach for discharge method.

UBI >> Contents 48 Copyright 2009 Texas Instruments All Rights Reserved www.msp430.ubi.pt Voltage Measurements (3/3)  Slope voltage measurement considerations:  The V CAREF selection should maximize V M range;  Accuracy of result depends on V CC ;  Capacitor charge selection for minimum error time

UBI >> Contents Lecture 5 Sigma-Delta (SD) converter, Slope converter & Comparator_A MSP430 Teaching Materials Texas Instruments Incorporated University.

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UBI >> Contents Lecture 5 Sigma-Delta (SD) converter, Slope converter & Comparator_A MSP430 Teaching Materials Texas Instruments Incorporated University.

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