1. George Mason University ECE 449 – Computer Design Lab Welcome to the ECE 449 Computer Design Lab Spring 2004

2. 2ECE 449 – Computer Design Lab Your TA – Tuesday session Milind M. Parelkar e-mail: mparelkar@gmu.edu Office hours: Monday 11:00am-1:00pm, Room 203

3. 3ECE 449 – Computer Design Lab Your TA – Thursday session Kamal Sayeed e-mail: ask4087@rit.edu Office hours: Wednesday 7-9pm, Room 203

4. 4ECE 449 – Computer Design Lab Lab meetings Time: Tuesday 4:30pm - 7:10pm Thursday 7:20pm - 10:00pm Venue: ST-II, Room 203 The first part of each meeting is reserved for a lecture given by the TA and the following hands-on session The second part of each meeting is reserved for the previous experiment demonstrations and the work on the new experiment

5. 5ECE 449 – Computer Design Lab Course description This course provides practical experience in designing digital circuits using VHDL for design description and FPGA devices for final implementation. Students learn to write an RTL code suitable for logic synthesis. Students gain “hands on” experience in every step of the circuit development.

6. 6ECE 449 – Computer Design Lab Design process (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Specification (Lab Experiments) VHDL description (Your Source Files) Functional simulation Post-synthesis simulation Synthesis

7. 7ECE 449 – Computer Design Lab Design process (2) Implementation Configuration Timing simulation On chip testing

8. 8ECE 449 – Computer Design Lab Expectations Practical knowledge of digital system design using VHDL (ECE 331, ECE 332) Knowledge gained in the ECE 447 course on Single-Chip Microcomputers would be useful (particularly in the last experiment)

9. 9ECE 449 – Computer Design Lab Lab policies Please refer to class website: ECE 449 Official Class Web Resources

10. 10ECE 449 – Computer Design Lab Lab experiments (Part I, Individual) Combinational Logic – 7 Segment LED, etc. January 27, 29 Sequential Logic – Blinking LEDs (Simulation) February 3, 5 Sequential Logic – Blinking LEDs (Testing) February 10, 12 Finite State Machine – Sequence Detector February 17, 19 Finite State Machine – Pump Controller February 24, 26

11. 11ECE 449 – Computer Design Lab Lab experiments (Part II, Dual) Programmable Pulse Generator March 16, 18 March 23, 25 VGA Signal Generator March 30, April 1 April 6, 8 Microcontroller Core April 13, 15 April 20, 22 April 27, 29

12. 12ECE 449 – Computer Design Lab Grading Lab Experiments (Part I)30% Midterm exam35% March 2, 4 Lab Experiments (Part II)35%

13. 13ECE 449 – Computer Design Lab Recommended Texts (1) Allen Dewey, Analysis and Design of Digital Systems with VHDL, 1997, PWS publishing, ISBN 0-534-95410-3 Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with VHDL Design, McGraw-Hill © 2000 Edition: 1 ISBN: 0072355964.

14. 14ECE 449 – Computer Design Lab Software ActiveHDL by Aldec used for design entry and simulation Synplify Pro by Synplicity used for logic synthesis Xilinx ISE by Xilinx Inc. used for implementation in Xilinx FPGA devices XESSTools by XESS used for testing and communication with the FPGA boards

15. 15ECE 449 – Computer Design Lab Hardware XSA-100 boards with Xilinx Spartan 2 FPGA 2S100tq144

16. 16ECE 449 – Computer Design Lab ?