1. Fall 2006 1 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Computer Organization Lecture 17 Controller design Microprogramming overview

2. Fall 2006 2 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering MIPS controller Inputs IR(31:25) Outputs From Lecture 12

3. Fall 2006 3 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering FSM architecture Present State NS Decoder Output Decoder Inputs Outputs Combo logic ROM MUX Combo logic ROM MUX Decoder Flip Flops

4. Fall 2006 4 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Ten one-bit outputs

5. Fall 2006 5 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Three two-bit outputs

6. Fall 2006 6 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering State diagram overview All instructions require IF, ID (2 clk’s) 2 Clk1-3 Clk

7. Fall 2006 7 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Full FSM state diagram Inputs:Op Outputs: 13 signals States: 10

8. Fall 2006 8 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering MDP16 controller Inputs IR(15:0) Outputs

9. Fall 2006 9 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Controller architecture PS flip- flops NSD  ROM Output Decoder Inputs Outputs  ROM contains microprogram

10. Fall 2006 10 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Controller overview Inputs: IR[0:15], EQ Outputs: ~15 signals Present state: 32-bits NSD or  ROM: 256x32

11. Fall 2006 11 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering MDP16 controller PSNSD Inputs Outputs

12. Fall 2006 12 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Controller outputs NameAssertedNot Asserted PCincPC is incremented by 1NA PCwrPC written with input numberNA EPCPC written to EPC addressNA IorDALU addresses memoryPC addresses memory MEMwrMemory is writtenMemory is read IRwrIR written with input numberNA MDRwrMDR written with input numberNA SPCwrSPC written with input numberNA PCsrcPC written with branch addressPC written with jump address

13. Fall 2006 13 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Controller outputs, continued. NameValueMeaning ALUa First ALU source 0101 PC R0 ALUb [0:1] Second ALU source 00 01 10 11 R1 IR [0:5] sign extended IR [0:5] zero extended Zero REGsrc Source for REG writes 0101 ALU MDR

14. Fall 2006 14 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Controller outputs, continued. NameValueMeaning REGrd [0:1] Register reads 00 01 10 11 R1 = $0, R0 = $0 R1 = $0, R0 = $1 R1 = $1, R0 = $0 R1 = $1, R0 = $1 REGwr [0:1] Register written 00 01 10 11 NA, none $0 $1 $1, $0

15. Fall 2006 15 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Controller outputs, continued. NameValueMeaning Funct [0:3]  Pgm control of ALU operation 0 1 2 3 4 - 7 8 9 A - F Add Sub And Or Reserved (Default to Add) Shift left logical Shift right logical Reserved (Default to Add)

16. Fall 2006 16 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Controller internals NameAssertedNot Asserted Branch Branch  Pgm to opcode addressUse  Pgm for next address RwrWrite value into REG arrayNA PCwrcondPC written with input number ONLY if EQ is asserted NA

17. Fall 2006 17 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Which output is asserted? ActionSignal(s) Increment the PCPCinc Write to the IRIRwr Write the branch address into the PC PCsrc=1 PCwr MDR data written to both $0 and $1 REGsrc=1 REGwr=11 Force the ALU to addFunc=0000

18. Fall 2006 18 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Microprogramming overview Review instructions, understand goals Determine state diagram Microprogram individual instructions –List tokens on one line –Repeat for remaining clocks Merge all instructions Test, test, test

19. Fall 2006 19 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Microprogramming steps  ROM contents defined by  assembler  ROM Source File Assembler Object File.upg.txtB2Logic MicroAsm

20. Fall 2006 20 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering MicroAsm Java application: MicroAsm.class, SavitchIn.class Microinstruction: free format, no fixed fields Requires input file: text-only, file.upg Creates output file: file.txt Errors: command line file name, file I/O, unrecognizable token Execution: BlueJ or DOS command line

21. Fall 2006 21 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering BlueJ execution Must pass input file name to main method

22. Fall 2006 22 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Output file defines control  ROM Address Data

23. Fall 2006 23 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering MDP16 op codes Op codeInstrClocks 0nop2 1R-fmt4 2sll4 3srl4 4lw5 5sw4

24. Fall 2006 24 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering MDP16 op codes, continued. Op codeInstrClocks 6beq3 7j3 Aaddi4 Bsubi4 Candi4 Dori4

25. Fall 2006 25 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering How many microinstructions? Op codeInstr 0nop 1R-fmt 2sll 3srl 4lw 5sw

26. Fall 2006 26 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering How many microinstructions? Op codeInstr 6beq 7j Aaddi Bsubi Candi Dori

27. Fall 2006 27 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Partial MDP16 state diagram A G C D E F H B JI Lw or Sw R-fmt Beq Jump Reset Lw Sw

28. Fall 2006 28 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering MDP16 state diagram IDID sll no p R- f m t swsw srllw add i be q j ori sub i and i IF Reset 1- 3 additional clocks 2 clocks

29. Fall 2006 29 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering

30. Fall 2006 30 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering Which output is asserted? ActionSignal(s) Increment the PCPCinc Write to the IRIRwr Write the branch address into the PC PCwr PCsrc MDR data written to both $0 and $1 REGsrc REGwr [0:1] = 11 Force the ALU to addFunct [0:3] = 0000

31. Fall 2006 31 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering How many microinstructions? Op codeInstr 0nop2 1R-fmt4 2sll4 3srl4 4lw5 5sw4

32. Fall 2006 32 EE 333 Lillevik 333f06-l17 University of Portland School of Engineering How many microinstructions? Op codeInstr 6beq3 7j3 Aaddi4 Bsubi4 Candi4 Dori4