1. Spring 2002INEL 4206 Microprocessors Lecture 4 1 Practical Universal Computers Prof. Bienvenido Velez Lecture 4 Bits Wires Gates Turing Machines

2. Spring 2002INEL 4206 Microprocessors Lecture 4 2 Outline The von Neumann Architecture –Big Idea: Interpretation –Stored program concept Designing a simple processor –Instruction Set Architecture –Data Paths –Control Unit

3. Spring 2002INEL 4206 Microprocessors Lecture 4 3 The (John) Von Neumann Architecture (late 40’s) I/O devices Central Processing Unit (CPU) Memory Allow communication with outside world Interprets instructions Stores both programs and data After 60 years … most processors still look like this!

4. Spring 2002INEL 4206 Microprocessors Lecture 4 4 The von Neumann Architecture Central Processing (CPU) I/O devices Central Processing Unit (CPU) Memory Control Unit (FSM) Data Paths Interconnected registers, muxes, decoders, … controlstatus active passive

5. Spring 2002INEL 4206 Microprocessors Lecture 4 5 The (John) Von Neuman Architecture The Memory Unit I/O devices Central Processing Unit (CPU) Memory 0 1ADD A 2SUB B 3JUMP 1 A B … N-1 word size address space

6. Spring 2002INEL 4206 Microprocessors Lecture 4 6 The (John) Von Neuman Architecture Stored Program Concept 0 1ADD A 2SUB B 3JUMP 1 A B … N-1 Program Instructions Program Data Programs and their data coexist in memory Processor, under program control, keeps track of what needs to be interpreted as instructions and what as data.

7. Spring 2002INEL 4206 Microprocessors Lecture 4 7 Easy I A Simple Accumulator Processor Instruction Set Architecture (ISA) Instruction Format (16 bits) IopcodeX 09101415 I = Indirect bit

8. Spring 2002INEL 4206 Microprocessors Lecture 4 8 NameOpcodeAction I=0 Action I=1 Comp 00 000 AC ← not ACAC <- not AC ShR 00 001 AC ← AC / 2 BrN 00 010 AC < 0 ⇒ PC ← XAC < 0 ⇒ PC ← MEM[X] Jump 00 011 PC ← XPC ← MEM[X] Store 00 100 MEM[X] ← ACMEM[MEM[X]] ← AC Load 00 101 AC ← MEM[X]AC ← MEM[MEM[X]] And 00 110 AC ← AC and XAC ← AC and MEM[X] Add 00 111 AC ← AC + XAC ← AC + MEM[X] Easy I A Simple Accumulator Processor Instruction Set Architecture (ISA) Instruction Set Easy all right … but universal it is!

9. Spring 2002INEL 4206 Microprocessors Lecture 4 9 Easy I A Simple Accumulator Processor Instruction Set Architecture (ISA) Accumulator (AC) is implicit operand to many instructions. No need to use instruction bits to specify one of the operands. More bits left for address and opcodes. Although simple, Easy I is universal. (given enough memory). Can you see this? Immediate bit specifies level of indirection for the location of the operand. I = 1: operand in X field (immediate). I=1 operand in memory location X (indirect). Some Immediate Observations on the Easy I ISA

10. Spring 2002INEL 4206 Microprocessors Lecture 4 10 ADDRESSBUSADDRESSBUS Easy I Data Paths Typically, designing a processor is an iterative (aka trial end error) process A0 A bus AB AC PC ALU DATABUSDATABUS DI

11. Spring 2002INEL 4206 Microprocessors Lecture 4 11 Processor Design Process Done Initial Data Path Design c-unit Measure Happy? Start yes no Review Data Path

12. Spring 2002INEL 4206 Microprocessors Lecture 4 12 Easy I Memory Interface CPU MEMORY address data word memory op {R,W,NOP}

13. Spring 2002INEL 4206 Microprocessors Lecture 4 13 Easy I Control Unit (Level 0 Flowcharts) Fetch Decode Execute Read next instruction Determine what it does and prepare to do it. Fetch operands. Do it! We will ignore indirect bit (assuming I = 0) for now

14. Spring 2002INEL 4206 Microprocessors Lecture 4 14 Easy I Control Unit (Level 1 Flowcharts) Fetch AoprSoprLoadStoreJumpBrN Level 1: Each box may take several CPU cycles to execute Reset What?

15. Spring 2002INEL 4206 Microprocessors Lecture 4 15 What makes a CPU cycle? CU Logic FSM logic state Data Paths Logic ALU, latches, memory Cycle time must accommodate signal propagation

16. Spring 2002INEL 4206 Microprocessors Lecture 4 16 Easy I Control Unit (Level 2 Flowcharts) Each box may take only one CPU cycle to execute 0 → PC reset1 PC → AO PC + 2 → PC reset2 RESET fetch Byte Addressable Can you tell why?

17. Spring 2002INEL 4206 Microprocessors Lecture 4 17 Easy I Control Unit (Level 3 Flowcharts) AO → EAB EDB → DI branch on opcode fetch FETCH 00 11x opcode aoprsoprloadstorebrnjump 00 00x00 10000 10100 01000 011 Opcode must be an input to CU’s sequential circuit Invariant At the beginning of the fetch cycle AO holds address of instruction to be fetched and PC points to following instruction Memory Bus Operation

18. Spring 2002INEL 4206 Microprocessors Lecture 4 18 Easy I Control Unit (Level 2 Flowcharts) DI → ABUS → ALUA AC → ALUB ALU → AC PC → AO PC + 2 → PC aopr AOpr fetch Restore fetch invariant

19. Spring 2002INEL 4206 Microprocessors Lecture 4 19 Easy I Control Unit (Level 2 Flowcharts) AC → ALUB ALU → AC PC → AO PC + 2 → PC sopr SOpr fetch

20. Spring 2002INEL 4206 Microprocessors Lecture 4 20 Easy I Control Unit (Level 2 Flowcharts) DI → ABUS → AO load1 DI → ABUS → ALUA ALU → AC PC → AO PC + 2 → PC load2 Load fetch AO → EAB EDB → DI load3

21. Spring 2002INEL 4206 Microprocessors Lecture 4 21 Easy I Control Unit (Level 2 Flowcharts) DI → ABUS → AO store1 store2 Store fetch AC → EDB AO → EAB PC → AO PC + 2 → PC

22. Spring 2002INEL 4206 Microprocessors Lecture 4 22 Easy I Control Unit (Level 2 Flowcharts) PC → AO PC + 2 → PC brn1 brn2 BrN fetch DI → PC DI → AO PC + 2 → PC AC:15 1 (AC<0) 0 (AC>0) Bit 15 of AC input to the CU’s sequential circuit Assume branch not taken. Allow AC:15 to propagate. Can we accomplish all this in 1 cycle? How?

23. Spring 2002INEL 4206 Microprocessors Lecture 4 23 Inside the Easy-I PC +2 Adder ABUS PC 0 pcsel pcis PC capable of loading and incrementing simultaneously 00 011011 0 1 PC

24. Spring 2002INEL 4206 Microprocessors Lecture 4 24 Easy I Control Unit (Level 2 Flowcharts) DI → PC DI → AO PC + 2 → PC jump JUMP fetch

25. Spring 2002INEL 4206 Microprocessors Lecture 4 25 Easy I Data Paths (with control points) le ADDRESSBUSADDRESSBUS A0 A bus AB AC PC ALU DATABUSDATABUS DI le op is sel le sel 01 0 1

26. Spring 2002INEL 4206 Microprocessors Lecture 4 26 Easy I Control Unit State Transition Table (Part I) Curr State opcodeAC:15Next State ALU op Mem OP PC sel PC is DI le AC le AO sel AO le EDB sel reset1xx xxxxreset2XXXNOP01X00X0X reset2xx xxxxfetchXXXNOP1010001X fetch00 00xxsoprXXXNOP11X10X0X fetch00 010xbrn1XXXRD11X10X0X fetch00 011xjumpXXXRD11X10X0X fetch00 100xstore1XXXRD11X10X0X fetch00 101xload1XXXRD11X10X0X fetch00 11xxaoprXXXRD11X10X0X aopr00 110xfetchANDNOP1010101X aopr00 111xfetchADDNOP1010101X sopr00 000xfetchNOTBNOP1010101X sopr00 001xfetchSHRBNOP1010101X

27. Spring 2002INEL 4206 Microprocessors Lecture 4 27 Easy I Control Unit State Transition Table (Part II) Current State opcodeAC:15Next State ALU op Mem OP PC sel PC is DI le AC le AO sel AO le EDB sel store1xx xxxxstore2XXXNOP11X0011X store2xx xxxxstore3XXXWR10100011 load1xx xxxxload2XXXNOP11X0011X load2xx xxxxload3XXXRD11X10X0X load3xx xxxxfetchXXXNOP1010101X brn1xx xxx0fetchXXXNOP1010001X brn1xx xxx1brn2XXXNOP1010001X brn2xx xxxxfetchXXXNOP1000011X jumpxx xxxxfetchXXXNOP1000011X CU with 14 states => 4 bits of state

28. Spring 2002INEL 4206 Microprocessors Lecture 4 28 Easy-I Control Unit – Some missing details StateEncoding reset1 0000 reset2 0001 fetch 0010 aopr 0011 sopr 0100 store1 0101 store2 0110 store3 0111 load1 1000 load2 1001 load3 1010 brn1 1011 brn2 1100 jump 1101 OperationCodeOutput A000A NOTB001not B AND010A and B ADD011A + B SHRB100B / 2 4-bit Encodings for States ALU Operation Table We know how to implement this ALU ! OperationCode NOP00 ReaD01 WRite10 Control Bus Operation Table

29. Spring 2002INEL 4206 Microprocessors Lecture 4 29 Easy I Control Unit State Transition Table (Part I) Curr State opcodeAC:15Next State ALU op Mem OP PC sel PC is DI le AC le AO sel AO le EDB sel 0000xx xxxx0001XXX0001X00X0X 0001xx xxxx0010XXX001010001X 001000 00xx0100XXX0011X10X0X 001000 010x1011XXX0111X10X0X 001000 011x1101XXX0111X10X0X 001000 100x0101XXX0111X10X0X 001000 101x1000XXX0111X10X0X 001000 11xx0011XXX0111X10X0X 001100 110x0010010001010101X 001100 111x0010011001010101X 010000 000x0010001001010101X 010000 001x0010100001010101X

30. Spring 2002INEL 4206 Microprocessors Lecture 4 30 Easy I Control Unit State Transition Table (Part II) Current State opcodeAC:15Next State ALU op Mem OP PC sel PC is DI le AC le AO sel AO le EDB sel 0101xx xxxx0110XXX0011X0011X 0110xx xxxx0111XXX10 100011 1000xx xxxx1001XXX0011X0011X 1001xx xxxx1010XXX0111X10X0X 1010xx xxxx0010XXX001010101X 1011xx xxx00010XXX001010001X 1011xx xxx11100XXX001010001X 1100xx xxxx0010XXX001000011X 1101xx xxxx0010XXX001000011X

31. Spring 2002INEL 4206 Microprocessors Lecture 4 31 Building the Easy-I C-Unit 2 Approaches Harwired –Apply well known sequential circuit techniques Micro-programmed –Treat state transition table as a program –Build a new abstraction layer The Microprogramming abstraction level A  program

32. Spring 2002INEL 4206 Microprocessors Lecture 4 32 Building the Easy-I C-Unit Hardwired Approach ROM state AC:15 DI 10 4 Data Paths Memory Unit control bus address bus data bus next state control point signals 5 Control Unit 11 2

33. Spring 2002INEL 4206 Microprocessors Lecture 4 33 Easy I Control Unit State Transition Table (Part II) 10-bit ROM address 18-bit ROM outputs Current State opcodeAC:15Next State ALU op Mem OP PC sel PC is DI le AC le AO sel AO le EDB sel 0101xx xxxx0110XXX00011X0011X 0110xx xxxx0111XXX01010100011 1000xx xxxx1001XXX00011X0011X 1001xx xxxx1010XXX00111X10X0X 1010xx xxxx0010XXX0001010101X 1011xx xxx00010XXX0001010001X 1011xx xxx11100XXX0001010001X 1100xx xxxx0010XXX0001000011X 1101xx xxxx0010XXX0001000011X 64 ROM Addresses with identical content

34. Spring 2002INEL 4206 Microprocessors Lecture 4 34 Programmable Logic Arrays

35. Spring 2002INEL 4206 Microprocessors Lecture 4 35

36. Spring 2002INEL 4206 Microprocessors Lecture 4 36 Building the Easy-I C-Unit 2 Approaches Harwired –Apply well known sequential circuit techniques Micro-programmed –Treat state transition table as a program –Build a new abstraction layer The Microprogramming abstraction level A  program

37. Spring 2002INEL 4206 Microprocessors Lecture 4 37 00110110 reset1reset201xx0001X00X0X reset2fetch01xx001010001X fetchxxxx00xx0011X10X0X store1store201xx0011X0011X store2fetch01xx10 100011 load1load201xx0011X0011X load2load301xx0111X10X0X load3fetch01xx0111X10X0X brn1xxxx11xx001010001X brn2fetch01xx001000011X jumpfetch01xx001000011X Building the Easy-I C-Unit Micro-programmed Approach Next State Bra nch ALU op Mem OP PC sel PC is DI le AC le AO sel AO le EDB sel Opcode Mapping opcode AC:15  Program (Comb Logic) DataPath Control 2  PC 01 fetch 4 brn2 unused

38. Spring 2002INEL 4206 Microprocessors Lecture 4 38 Finding the first execute state Combinational Logic InstructionOpcodeAC:15First Execute State Comp 00 000 xsopr ShR 00 001 xsopr BrN 00 010 1brn1 Jump 00 011 xjump Store 00 100 xstore1 Load 00 101 xload1 And 00 110 xaopr Add 00 111 xaopr Opcode Mapping opcode

39. Spring 2002INEL 4206 Microprocessors Lecture 4 39 Summary Instruction Set Architecture Processor Implementation What we know? From To How do we get here In the first place? What Next? Instruction Set Design