2. Computer Organization Lecture Set – 05.2 Chapter 5 Huei-Yung Lin

3. H.Y. Lin, CCUEE Computer Organization 2 Outline - Processor Implementation Overview Single-Cycle Implementation Multi-Cycle Implementation  1.Analyze instruction set; get datapath requirements 2.Select datapath components and establish clocking methodology 3.Assemble datapath that meets requirements 4.Determine control signal values for each instruction 5.Assemble control logic to generate control signals Pipelined Implementation

4. H.Y. Lin, CCUEE Computer Organization 3 Outline - Multicycle Design Overview  Datapath Design Controller Design Microprogramming Exceptions Performance Considerations

5. H.Y. Lin, CCUEE Computer Organization 4 Multicycle Execution - Key Idea Break instruction execution into multiple cycles One clock cycle for each major task 1.Instruction Fetch 2.Instruction Decode and Register Fetch 3.Execution, memory address computation, or branch computation 4.Memory access / R-type instruction completion 5.Memory read completion Share hardware to simplify datapath

6. H.Y. Lin, CCUEE Computer Organization 5 Characteristics of Multicycle Design Instructions take more than one cycle  Some instructions take more cycles than others  Clock cycle is shorter than single-cycle clock Reuse of major components simplifies datapath  Single ALU for all calculations  Single memory for instructions and data  But, added registers needed to store values across cycles Control Unit Implemented w/ State Machine  Control signals no longer a function of just the instruction

7. H.Y. Lin, CCUEE Computer Organization 6 (Equivalent to Book Fig. 5.25, p. 318) Multicycle Datapath - High-Level View

8. H.Y. Lin, CCUEE Computer Organization 7 Review: Steps in Processor Design 1.Analyze instruction set; get datapath requirements 2.Select datapath components and establish clocking methodology 3.Assemble datapath that meets requirements 4.Determine control signal values for each instruction 5.Assemble control logic to generate control signals

9. H.Y. Lin, CCUEE Computer Organization 8 Review: Register Transfers Instruction Fetch Instruction <= MEM[PC]; PC = PC + 4; Instruction Execution Instr.Register Transfers add R[rd] <= R[rs] + R[rt]; sub R[rd] <= R[rs] - R[rt]; and R[rd] <= R[rs] & R[rt]; or R[rd] <= R[rs] | R[rt]; lw R[rt] <= MEM[R[rs] + s_extend(offset)]; sw MEM[R[rs] + sign_extend(offset)] <= R[rt];PC <= PC + 4 beq if (R[rs] == R[rt]) then PC <- PC+4 + s_extend(offset<<2) else PC <= PC + 4 j PC <= upper(PC)@(address << 2) Key idea: break into multiple cycles!

10. H.Y. Lin, CCUEE Computer Organization 9 Multicycle Execution Steps 1.Instruction Fetch 2.Instruction Decode and Register Fetch (and branch target calculation) 3.One of the following:  Execute R-Type Instruction OR  Calculate memory address for load/store OR  Perform comparison for branch 4.Memory access for load/store OR R-type instruction completion (save result) 5.Memory read completion (save result - load only)

11. H.Y. Lin, CCUEE Computer Organization 10 Summary - Multicycle Execution Instructions take between 3 and 5 clock cycles (Book Fig. 5.30, p. 329) (1) (2) (3) (4) (5) New registers needed to store values across clock steps!

12. H.Y. Lin, CCUEE Computer Organization 11 IR = Memory[PC]; PC = PC + 4; 4 PC + 4 Multicycle Execution Step (1) Instruction Fetch

13. H.Y. Lin, CCUEE Computer Organization 12 Multicycle Execution Step (2) Instruction Decode and Register Fetch A = Reg[IR[25-21]];(A = Reg[rs]) B = Reg[IR[20-15]];(B = Reg[rt]) ALUOut = (PC + sign-extend(IR[15-0]) << 2) Branch Target Address Reg[rs] Reg[rt] PC + 4

14. H.Y. Lin, CCUEE Computer Organization 13 Multicycle Execution Steps (3) Memory Reference Instructions ALUOut = A + sign-extend(IR[15-0]); Mem. Address Reg[rs] Reg[rt] PC + 4

15. H.Y. Lin, CCUEE Computer Organization 14 Multicycle Execution Steps (3) ALU Instruction (R-Type) ALUOut = A op B R-Type Result Reg[rs] Reg[rt] PC + 4

16. H.Y. Lin, CCUEE Computer Organization 15 Multicycle Execution Steps (3) Branch Instructions if (A == B) PC = ALUOut; Branch Target Address Reg[rs] Reg[rt] Branch Target Address

17. H.Y. Lin, CCUEE Computer Organization 16 Multicycle Execution Step (3) Jump Instruction PC = PC[31-28] concat (IR[25-0] << 2) Jump Address Reg[rs] Reg[rt] Branch Target Address

18. H.Y. Lin, CCUEE Computer Organization 17 Multicycle Execution Steps (4) Memory Access - Read (lw) MDR = Memory[ALUOut]; Mem. Data PC + 4 Reg[rs] Reg[rt] Mem. Address

19. H.Y. Lin, CCUEE Computer Organization 18 Multicycle Execution Steps (4) Memory Access - Write (sw) Memory[ALUOut] = B; PC + 4 Reg[rs] Reg[rt]

20. H.Y. Lin, CCUEE Computer Organization 19 Multicycle Execution Steps (4) ALU Instruction (R-Type) Reg[IR[15:11]] = ALUOUT R-Type Result Reg[rs] Reg[rt] PC + 4

21. H.Y. Lin, CCUEE Computer Organization 20 Multicycle Execution Steps (5) Memory Read Completion (lw) Reg[IR[20-16]] = MDR; PC + 4 Reg[rs] Reg[rt] Mem. Data Mem. Address

22. H.Y. Lin, CCUEE Computer Organization 21 Summary - Multicycle Execution Instructions take between 3 and 5 clock cycles (Book Fig. 5.30, p. 329)

23. H.Y. Lin, CCUEE Computer Organization 22 Full Multicycle Datapath (Equivalent to Book Fig. 5.27, p. 322 without ALU control)

24. H.Y. Lin, CCUEE Computer Organization 23 Full Multicycle Implementation (Equivalent to Book Fig. 5.28, p. 323)

25. H.Y. Lin, CCUEE Computer Organization 24 Review: Steps in Processor Design 1.Analyze instruction set; get datapath requirements 2.Select datapath components and establish clocking methodology 3.Assemble datapath that meets requirements 4.Determine control signal values for each instruction 5.Assemble control logic to generate control signals

26. H.Y. Lin, CCUEE Computer Organization 25 Multicycle Execution Step (1) Fetch IR = Memory[PC]; PC = PC + 4; 1 0 1 0 1 0 X 0 X 0 010 1

27. H.Y. Lin, CCUEE Computer Organization 26 Multicycle Execution Step (2) Instruction Decode and Register Fetch A = Reg[IR[25-21]];(A = Reg[rs]) B = Reg[IR[20-15]];(B = Reg[rt]) ALUOut = (PC + sign-extend(IR[15-0]) << 2) 0 0 X 0 0 X 3 0 X X 010 0

28. H.Y. Lin, CCUEE Computer Organization 27 0 X Multicycle Execution Steps (3) Memory Reference Instructions ALUOut = A + sign-extend(IR[15-0]); X 2 0 0 X 0 1 X 010 0

29. H.Y. Lin, CCUEE Computer Organization 28 Multicycle Execution Steps (3) ALU Instruction (R-Type) ALUOut = A op B 0 X X 0 0 0 X 0 1 X ??? 0

30. H.Y. Lin, CCUEE Computer Organization 29 1 if Zero=1 Multicycle Execution Steps (3) Branch Instructions if (A == B) PC = ALUOut; 0 X X 0 0 X 0 1 1 011 0

31. H.Y. Lin, CCUEE Computer Organization 30 Multicycle Execution Step (3) Jump Instruction PC = PC[21-28] concat (IR[25-0] << 2) 0 X X X 0 1 X 0 X 2 XXX 0

32. H.Y. Lin, CCUEE Computer Organization 31 Multicycle Execution Steps (4) Memory Access - Read (lw) MDR = Memory[ALUOut]; 0 X X X 1 0 1 0 X X XXX 0

33. H.Y. Lin, CCUEE Computer Organization 32 Multicycle Execution Steps (4) Memory Access - Write (sw) Memory[ALUOut] = B; 0 X X X 0 0 1 1 X X XXX 0

34. H.Y. Lin, CCUEE Computer Organization 33 1 0 0 X 0 X 0 XXX X X 1 1 Multicycle Execution Step (4) ALU Instruction (R-Type) Reg[IR[15:11]] = ALUOut;(Reg[Rd] = ALUOut)

35. H.Y. Lin, CCUEE Computer Organization 34 Multicycle Execution Steps (5) Memory Read Completion (lw) Reg[IR[20-16]] = MDR; 1 0 0 X 0 0 X 0 X X XXX 0

36. H.Y. Lin, CCUEE Computer Organization 35 Review: Steps in Processor Design 1.Analyze instruction set; get datapath requirements 2.Select datapath components and establish clocking methodology 3.Assemble datapath that meets requirements 4.Determine control signal values for each instruction 5.Assemble control logic to generate control signals

37. H.Y. Lin, CCUEE Computer Organization 36 Full Multicycle Implementation

38. H.Y. Lin, CCUEE Computer Organization 37 Multicycle Control Unit Review: single-cycle implementation  All control signals can be determined by current instruction + condition  Implemented in combinational logic Multicycle implementation is different  Control signals depend on current instruction which clock cycle is currently being executed  Implemented as Finite State Machine (FSM) OR Microprogrammed Implementation - “ stylized FSM ”

39. H.Y. Lin, CCUEE Computer Organization 38 Review - Finite State Machines What’s in the Finite State Machine  Combinational Logic  Storage Elements (Flip-flops) Inputs Outputs Current State Next State

40. H.Y. Lin, CCUEE Computer Organization 39 Review - Finite State Machines Behavior characterized by  States - unique values of flip-flops e.g., “ 101 ”  Transitions between states, depending on current state inputs  Output values, depending on current state inputs Describing FSMs:  State Diagrams  State Transition Tables

41. H.Y. Lin, CCUEE Computer Organization 40 Review - State Diagrams "Bubbles" - states Arrows - transition edges labeled with condition expressions Example: Car Alarm arm door honk clk f clk = 1Hz IDLE BEEP Honk=1 WAIT ARMDOOR ARM ARM’ ARM’ + ARMDOOR’ = ARM’ + DOOR’

42. H.Y. Lin, CCUEE Computer Organization 41 State Transition Table Transition List - lists edges in State Diagram PSConditionNSOutput IDLEARM' + DOOR'IDLE0 IDLEARM*DOORBEEP0 BEEPARMWAIT1 BEEPARM'IDLE1 WAITARMBEEP0 WAITARM'IDLE0 IDLE BEEP Honk=1 WAIT ARMDOOR ARM ARM’ ARM’ + ARMDOOR’ = ARM’ + DOOR’

43. H.Y. Lin, CCUEE Computer Organization 42 State Machine Design Traditional Approach:  Create State Diagram  Create State Transition Table  Assign State Codes  Write Excitation Equations & Minimize Modern Approach  Enter FSM Description into CAD program  Synthesize implementation of FSM

44. H.Y. Lin, CCUEE Computer Organization 43 FSM Control Unit Implementation FSM Inputs:  Clock  Instruction register op field FSM Outputs: control signals for datapath  Enable signals: Register file, Memory, PC, MDR, and IR  Multiplexer signals: ALUSrcA, ALUSrcB, etc.  ALUOp signal - used for ALU Control as in single-cycle implementation

45. H.Y. Lin, CCUEE Computer Organization 44 Enable Control Signals  Asserted (true) in a state if they appear in the state bubble  Assumed Deasserted (false) in a state if they do not appear in the state bubble Multiplexer/ALU Control Signals  Asserted with a given value in a state if they appear in a state bubble  Assumed Don ’ t Care if they do not appear in the state bubble See Figures 5.32 - 5.36 3 MemRead IorD = 0 Memory access (Op=‘LW’) Enable signal Multiplexer signal State name Transition from previous state (conditioanl) Transition to next state (unconditioanl) Describing Controller Function in State Diagrams - Conventions

46. H.Y. Lin, CCUEE Computer Organization 45 Multicycle Control - Full State Diagram

47. H.Y. Lin, CCUEE Computer Organization 46 State 8 Branch State (OP = ‘BEQ’) State 6 Execution States (OP = ‘R-Type’) State 2 Mem. Ref States (Op = ‘LW’ or Op = ‘SW’) MemRead ALUSrcA = 0 IorD = 0 IRWrite ALUSrcB = 01 ALUOp = 00 PCWrite PCSource = 00 State 0 Instruction Fetch Start State 1 Instruction Decode / Register Fetch State 9 Jump State (OP = ‘J’) ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 Control FSM - Instruction Fetch / Decode States

48. H.Y. Lin, CCUEE Computer Organization 47 (OP = ‘LW’) State 3 Memory Access State 4 Write-back step State 5 Memory Access (OP = ‘SW’) Memory Address ComputationState 2 from State 1 (OP = ‘LW’ OR OP = ‘SW’) to State 0 ALUSrcA = 1 ALUSrcB = 10 ALUOp = 00 MemRead IorD = 1 MemWrite IorD = 1 RegWrite MemToReg=1 RegDst = 0 Control FSM - Memory Reference States

49. H.Y. Lin, CCUEE Computer Organization 48 Control FSM - R-Type States State 7 R-type completion to State 0 State 6 from State 1 (OP = R-Type) Execution ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 RegDst = 1 RegWrite MemtoReg = 0

50. H.Y. Lin, CCUEE Computer Organization 49 Control FSM - Branch State State 8 Branch Completion from State 1 (OP = ‘BEQ’) to State 0 ALUSrcA = 1 ALUSrcB = 00 ALUOp = 01 PCWriteCond PCSource = 01

51. H.Y. Lin, CCUEE Computer Organization 50 Control FSM - Jump State State 9 Jump Completion from State 1 (OP = ‘J’) to State 0 PCWrite PCSource = 10

52. H.Y. Lin, CCUEE Computer Organization 51 Controller Implementation Typical Implementation: Figure 5-37, p. 338 Variations  Random logic  PLA  ROM address lines = inputs data lines = outputs contents = “truth table” Datapath control outputs Inputs from Instr. Reg (opcode) Combinational Control Logic State Next State

53. H.Y. Lin, CCUEE Computer Organization 52 What is the CPI of the Multicycle Implementation? Using measured instruction mix from SPECINT2000 lw5 cycles25% sw4 cycles10% R-type4 cycles52% branch3 cycles11% jump3 cycles2% What is the CPI?  CPI = (5 cycles * 0.25) + (4 cycles * 0.10) + (4 cycles * 0.53) + (3 cycles * 0.11) + (3 cycles * 0.02)  CPI = 4.12 cycles per instruction Performance of a Multicycle Implementation

54. H.Y. Lin, CCUEE Computer Organization 53 Performance Continued Assuming a 200ps clock, what is average execution time/instruction?  Sec/Instr = 4.12 CPI * 200ps/cycle) = 824ps/instr How does this compare to the Single-Cycle Case?  Sec/Instr = 1 CPI * 600ps/cycle = 600ps/instr  Single-Cycle is 1.38 times faster than Multicycle Why is Single-Cycle faster than Multicycle?  Branch & jump are the same speed (600ps vs 600ps)  R-type & store are faster (600ps vs 800ps)  Load word is faster (600ps vs 1000ps)

55. H.Y. Lin, CCUEE Computer Organization 54 Multicycle Example Problem Extend the design to implement the “jr” (jump register) instruction: jr rsPC = Reg[rs] Format: Steps: 1.Review instruction requirements (register transfer) 2.Modify datapath 3.Modify control logic 0 rs00 8 0 6 bits5 bits 6 bits

56. H.Y. Lin, CCUEE Computer Organization 55 Reg[rs] Example Problem: Datapath What needs to be changed? 3 2 1 0

57. H.Y. Lin, CCUEE Computer Organization 56 Example Problem: Control What needs to be changed? PCWrite PCSource = 11 (OP = ‘JR‘)

58. H.Y. Lin, CCUEE Computer Organization 57 Exceptions - “ Stuff Happens ” Definition: "unexpected change in control flow" Used to handle runtime errors  Overflow  Undefined Instruction  Hardware malfunction Used to handle external events, "service" functions  Interrupts - external I/O Device request  Page fault - virtual memory  System call - user request for OS action

59. H.Y. Lin, CCUEE Computer Organization 58 Example: Undefined Instructions (OP ≠ R-Type OP≠LW, OP–W, OP≠BEQ) What happens here ????

60. H.Y. Lin, CCUEE Computer Organization 59 What Happens During an Exception Save user state – register values, etc. Take action to handle exception Restore user state and continue execution if possible (e.g., emulate undefined instr.) Exception: undefined instruction Return from exception user program add.s f0,f1,f2 srl r1,r2,2 beq r0,r1,L sub r5,r3,r2 add r5,r4,r3 bne r4,r3,L2 add r3,r1,r2 Exception Handler (System) rfe

61. H.Y. Lin, CCUEE Computer Organization 60 Two exceptions (for now):  Undefined instruction  Arithmetic overflow Add registers to architecture to save state  EPC - Exception Program Counter (32 bits)  Cause - records cause of exception (32 bits) Undefined instruction: Cause <- 0 Arithmetic overflow: Cause <- 1 Alternatives used by other architectures Save PC on stack Communicate exception type using Exception Vector Adding Exceptions to the Multicycle Processor

62. H.Y. Lin, CCUEE Computer Organization 61 Implementing Exceptions Add datapath components - Figure 5.39  ExceptionPC (EPC) - stores PC of offending instruction  Cause Register - records the cause of the exception Modify control - Figures 5.40  Undefined Instruction - state 1 (Instruction decode)  Overflow - state 7 (R-type completion)

63. H.Y. Lin, CCUEE Computer Organization 62 Implementing Exceptions Datapath modifications  Calculate address of offending instruction (PC-4) and store in EPC  Store 0 or 1 in Cause  Add overflow output from ALU (described in Ch. 4)  Assign "8000180 hex " to PC - fixed location of handler Control modifications  Undefined instruction: add ” default" branch to Instruction Fetch state  Overflow: test after execution state for R-type instructions

64. H.Y. Lin, CCUEE Computer Organization 63 Adding Exception Support to Datapath

65. H.Y. Lin, CCUEE Computer Organization 64 IntCause = 0 CauseWrite ALUSrcA = 0 ALUSrcB = 01 ALUOp = 01 EPCWRITE PCWrite PCSource=11 State 10 Undefined Instruction State 0 ALUSrcA = 0 ALUSrcB = 11 ALUOp = 00 State 1 Instruction Decode / Register Fetch State 9 Jump State State 8 Branch State State 6 Execution States State 2 Mem. Ref States (OP = ‘J’) (OP = ‘BEQ’) (OP = ‘R-Type’) (Op = ‘LW’ or Op = ‘SW’) from State 0 (OP = Other) Adding Exception Support to Control - Undefined Instruction

66. H.Y. Lin, CCUEE Computer Organization 65 IntCause = 1 CauseWrite ALUSrcA = 0 ALUSrcB = 01 ALUOp = 01 EPCWRITE PCWrite PCSource=11 State 10 Overflow State 0 Overflow Note: requires storage of overflow condition from previous state ALUSrcA = 1 ALUSrcB = 00 ALUOp = 10 State 6 RegDst = 1 RegWrite MemtoReg = 0 State 7 R-type completion from State 1 (OP = R-Type) to State 0 Execution No Overflow Adding Exception Support to Control - Arithmetic Overflow

67. H.Y. Lin, CCUEE Computer Organization 66 What Makes Exceptions Hard The “ real ” MIPS architecture requires that instruction causing exception must have "no effect" Implication: undo effects of instruction  decrement PC  prevent storage of result during R-type instruction What about “ recursive ” exceptions?  Must add instructions to save exception registers on stack  Disable exceptions / interrupts until registers saved  More details in Appendix A (A.7)

68. H.Y. Lin, CCUEE Computer Organization 67 Summary - Exceptions Must consider as part of overall design Must find "convenient" places to detect exceptions Must find way to cleanly return from exception Must keep control “ small and fast ” Much harder in pipelined implementations!